2-10 Revision 11 Combinatorial Cells Contribution鈥擯C-CELL
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A3PN060-Z2VQ100I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 32/114闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA NANO 60K GATES 100-VQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� ProASIC3 nano
RAM 浣嶇附瑷�(j矛)锛� 18432
杓稿叆/杓稿嚭鏁�(sh霉)锛� 71
闁€鏁�(sh霉)锛� 60000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 100-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-VQFP锛�14x14锛�
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ProASIC3 nano DC and Switching Characteristics
2-10
Revision 11
Combinatorial Cells Contribution鈥擯C-CELL
PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs鈥攇uidelines are provided in Table 2-12 on page 2-11.
FCLK is the global clock signal frequency.
Routing Net Contribution鈥擯NET
PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs鈥攇uidelines are provided in Table 2-12 on page 2-11.
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution鈥擯INPUTS
PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
2 is the I/O buffer toggle rate鈥攇uidelines are provided in Table 2-12 on page 2-11.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution鈥擯OUTPUTS
POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
2 is the I/O buffer toggle rate鈥攇uidelines are provided in Table 2-12 on page 2-11.
1 is the I/O buffer enable rate鈥攇uidelines are provided in Table 2-13 on page 2-11.
FCLK is the global clock signal frequency.
RAM Contribution鈥擯MEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3
NBLOCKS is the number of RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
2 is the RAM enable rate for read operations.
FWRITE-CLOCK is the memory write clock frequency.
3 is the RAM enable rate for write operations鈥攇uidelines are provided in Table 2-13 on page 2-11.
PLL Contribution鈥擯PLL
PPLL = PDC4 + PAC13 * FCLKOUT
FCLKOUT is the output clock frequency.1
1.
The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
A3PN060-Z2VQG100I IC FPGA NANO 60K GATES 100-VQFP
AYM30DTAH-S189 CONN EDGECARD 60POS R/A .156 SLD
ASM30DTAH-S189 CONN EDGECARD 60POS R/A .156 SLD
AGM30DTAH-S189 CONN EDGECARD 60POS R/A .156 SLD
AYM30DTAD-S189 CONN EDGECARD 60POS R/A .156 SLD
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鍙冩暩(sh霉)鎻忚堪
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