2-70 Revision 11 Embedded FlashROM Characteristics Timing Characteristics Figure 2-39
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A3PN060-1VQG100I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 98/114闋�
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鎻忚堪锛� IC FPGA NANO 60K GATES 100-VQFP
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绯诲垪锛� ProASIC3 nano
RAM 浣嶇附瑷堬細 18432
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闁€鏁�(sh霉)锛� 60000
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ProASIC3 nano DC and Switching Characteristics
2-70
Revision 11
Embedded FlashROM Characteristics
Timing Characteristics
Figure 2-39 Timing Diagram
A0
A1
tSU
tHOLD
tSU
tHOLD
tSU
tHOLD
tCKQ2
CLK
Address
Data
D0
D1
Table 2-77 Embedded FlashROM Access Time
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
鈥�2
鈥�1
Std.
Units
tSU
Address Setup Time
0.53
0.61
0.71
ns
tHOLD
Address Hold Time
0.00
ns
tCK2Q
Clock to Out
16.23
18.48
21.73
ns
FMAX
Maximum Clock Frequency
15.00
MHz
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