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ProASIC3 nano DC and Switching Characteristics
2-40
Revision 11
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Clear
Figure 2-11 Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Enable
CLK
Pad
Out
CLK
Enable
CLR
Data_out
Data
Y
AA
EOUT
DOUT
Core
Array
DQ
DFN1E1C1
E
CLR
DQ
DFN1E1C1
E
CLR
DQ
DFN1E1C1
E
CLR
D_Enable
BB
CC
DD
EE
FF
GG
LL
HH
JJ
KK
CLKBUF
INBUF
TRIBUF
INBUF
CLKBUF
INBUF
Data Input I/O Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
Data Output Register and
Enable Output Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
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PDF鎻忚堪
GMC65DRTI-S13 CONN EDGECARD 130POS .100 EXTEND
HBC60DRAN CONN EDGECARD 120PS R/A .100 SLD
HBC60DRAH CONN EDGECARD 120PS R/A .100 SLD
AGL030V5-QNG48 IC FPGA 1KB FLASH 30K 48-QFN
A3PN030-Z1QNG68 IC FPGA NANO 30K GATES 68-QFN
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