Revision 13 2-9 Power Calculation Methodology This section describes a simplified method to estimate power consumptio" />
參數(shù)資料
型號： A3PE600-PQG208I
廠商： Microsemi SoC
文件頁數(shù)： 79/162頁
文件大?。?/td> 0K
描述： IC FPGA 600000 GATES 208-PQFP
標準包裝： 24
系列： ProASIC3E
RAM 位總計： 110592
輸入/輸出數(shù)： 147
門數(shù)： 600000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
ProASIC3E Flash Family FPGAs
Revision 13
2-9
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in the Libero SoC software.
The power calculation methodology described below uses the following variables:
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-11 on
Enable rates of output buffers—guidelines are provided for typical applications in Table 2-12 on
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-12 on page 2-11. The calculation should be repeated for each clock domain defined in the
design.
Methodology
Total Power Consumption—PTOTAL
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
PDYN is the total dynamic power consumption.
Total Static Power Consumption—PSTAT
PSTAT = PDC1 + NINPUTS * PDC2 + NOUTPUTS * PDC3
NINPUTS is the number of I/O input buffers used in the design.
NOUTPUTS is the number of I/O output buffers used in the design.
Total Dynamic Power Consumption—PDYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution—PCLOCK
PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided in the
"Spine Architecture" section of the Global Resources chapter in the ProASIC3E FPGA Fabric
.
NROW is the number of VersaTile rows used in the design—guidelines are provided in the
"Spine Architecture" section of the Global Resources chapter in the ProASIC3E FPGA Fabric
.
FCLK is the global clock signal frequency.
NS-CELL is the number of VersaTiles used as sequential modules in the design.
PAC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution—PS-CELL
PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a
multi-tile sequential cell is used, it should be accounted for as 1.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on
.
FCLK is the global clock signal frequency.
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