2-10 Revision 13 Combinatorial Cells Contribution鈥擯C-CELL
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ProASIC3E DC and Switching Characteristics
2-10
Revision 13
Combinatorial Cells Contribution鈥擯C-CELL
PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs鈥攇uidelines are provided in Table 2-11 on
.
FCLK is the global clock signal frequency.
Routing Net Contribution鈥擯NET
PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs鈥攇uidelines are provided in Table 2-11 on
.
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution鈥擯INPUTS
PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
2 is the I/O buffer toggle rate鈥攇uidelines are provided in Table 2-11 on page 2-11.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution鈥擯OUTPUTS
POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
2 is the I/O buffer toggle rate鈥攇uidelines are provided in Table 2-11 on page 2-11.
1 is the I/O buffer enable rate鈥攇uidelines are provided in Table 2-12 on page 2-11.
FCLK is the global clock signal frequency.
RAM Contribution鈥擯MEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3
NBLOCKS is the number of RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
2 is the RAM enable rate for read operations鈥攇uidelines are provided in Table 2-12 on
.
FWRITE-CLOCK is the memory write clock frequency.
3 is the RAM enable rate for write operations鈥攇uidelines are provided in Table 2-12 on
.
PLL Contribution鈥擯PLL
PPLL = PAC13 + PAC14 * FCLKOUT
FCLKOUT is the output clock frequency.1
1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution.
鐩搁棞(gu膩n)PDF璩囨枡
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