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寤犲晢锛� Microsemi SoC
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鏂囦欢澶�?銆�?/td> 0K
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绯诲垪锛� ProASIC3E
RAM 浣嶇附瑷堬細 110592
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闁€鏁�(sh霉)锛� 600000
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瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
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灏佽/澶栨锛� 256-LBGA
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ProASIC3E Flash Family FPGAs
Revision 13
2-35
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 2-41 Minimum and Maximum DC Input and Output Levels
1.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA3
Max.
mA3 A4 A4
2 mA
鈥�0.3 0.30 * VCCI 0.7 * VCCI
3.6
0.25 * VCCI
0.75 * VCCI
2
16
13
10 10
4 mA
鈥�0.3 0.30 * VCCI 0.7 * VCCI
3.6
0.25 * VCCI
0.75 * VCCI
4
33
25
10 10
6 mA
鈥�0.3 0.30 * VCCI 0.7 * VCCI
3.6
0.25 * VCCI
0.75 * VCCI
6
39
32
10 10
8 mA
鈥�0.3 0.30 * VCCI 0.7 * VCCI
3.6
0.25 * VCCI
0.75 * VCCI
8
55
66
10 10
12 mA
鈥�0.3 0.30 * VCCI 0.7 * VCCI
3.6
0.25 * VCCI
0.75 * VCCI
12 12
55
66
10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where 鈥�0.3 V< VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100掳C junction temperature) and maximum voltage.
4. Currents are measured at 85掳C junction temperature.
5. Software default selection highlighted in gray.
Figure 2-10 AC Loading
Table 2-42 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (typ.) (V)
CLOAD (pF)
0
1.5
0.75
鈥�
35
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Test Point
Enable Path
Datapath
35 pF
R = 1 k
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
鐩搁棞(gu膩n)PDF璩囨枡
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A3PE600-FGG256 IC FPGA 600000 GATES 256-FBGA
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ABC60DRTS-S13 CONN EDGECARD 120POS .100 EXTEND
RMC50DRXI CONN EDGECARD 100PS DIP .100 SLD
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A3PE600-FG484 鍔熻兘鎻忚堪:IC FPGA 600000 GATES 484-FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3E 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
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