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鍨嬭櫉锛� A3PE600-1FGG256
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 13/162闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 600000 GATES 256-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� ProASIC3E
RAM 浣嶇附瑷�(j矛)锛� 110592
杓稿叆/杓稿嚭鏁�(sh霉)锛� 165
闁€鏁�(sh霉)锛� 600000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 256-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 256-FPBGA锛�17x17锛�
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ProASIC3E Flash Family FPGAs
Revision 13
1-5
SRAM and FIFO
ProASIC3E devices have embedded SRAM blocks along their north and south sides. Each variable-
aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256脳18, 512脳9,
1k脳4, 2k脳2, and 4k脳1 bits. The individual blocks have independent read and write ports that can be
configured with different bit widths on each port. For example, data can be sent through a 4-bit port and
read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port
(ROM emulation mode) using the UJTAG macro.
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM
block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width
and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and
Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control
unit contains the counters necessary for generation of the read and write address pointers. The
embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
ProASIC3E devices provide designers with very flexible clock conditioning capabilities. Each member of
the ProASIC3E family contains six CCCs, each with an integrated PLL.
The six CCC blocks are located at the four corners and the centers of the east and west sides.
To maximize user I/Os, only the center east and west PLLs are available in devices using the PQ208
package. However, all six CCC blocks are still usable; the four corner CCCs allow simple clock delay
operations as well as clock spine access.
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz
Clock delay adjustment via programmable and fixed delays from 鈥�7.56 ns to +11.12 ns
2 programmable delay types for clock skew minimization
Clock frequency synthesis
Additional CCC specifications:
Internal phase shift = 0掳, 90掳, 180掳, and 270掳. Output phase shift depends on the output divider
configuration.
Output duty cycle = 50% 卤 1.5% or better
Low output jitter: worst case < 2.5% 脳 clock period peak-to-peak period jitter when single global
network used
Maximum acquisition time = 300 s
Low power consumption of 5 mW
Exceptional tolerance to input period jitter鈥� allowable input jitter is up to 1.5 ns
Four precise phases; maximum misalignment between adjacent phases of 40 ps 脳 (350 MHz /
fOUT_CCC)
Global Clocking
ProASIC3E devices have extensive support for multiple clocking domains. In addition to the CCC and
PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid
distribution of high fanout nets.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
M1A3P400-1PQ208I IC FPGA 1KB FLASH 400K 208-PQFP
A3P400-1PQG208I IC FPGA 1KB FLASH 400K 208-PQFP
M1A3P400-1PQG208I IC FPGA 1KB FLASH 400K 208-PQFP
IDT71256SA25TPG IC SRAM 256KBIT 25NS 28DIP
IDT71256SA20TPG IC SRAM 256KBIT 20NS 28DIP
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A3PE600-1FGG256I 鍔熻兘鎻忚堪:IC FPGA 600000 GATES 256-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3E 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
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