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鍨嬭櫉锛� A3PE600-1FG256I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 121/162闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 600000 GATES 256-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� ProASIC3E
RAM 浣嶇附瑷堬細 110592
杓稿叆/杓稿嚭鏁�(sh霉)锛� 165
闁€鏁�(sh霉)锛� 600000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
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ProASIC3E Flash Family FPGAs
Revision 13
2-47
SSTL3 Class II
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support
Class II. This provides a differential amplifier input buffer and a push-pull output buffer.
Timing Characteristics
Table 2-75 Minimum and Maximum DC Input and Output Levels
SSTL3 Class II
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA1
Max.
mA1
A2 A2
21 mA
鈥�0.3 VREF 鈥� 0.2 VREF + 0.2
3.6
0.5
VCCI 鈥� 0.9 21 21
109
103
10 10
Notes:
1. Currents are measured at high temperature (100掳C junction temperature) and maximum voltage.
2. Currents are measured at 85掳C junction temperature.
Figure 2-21 AC Loading
Table 2-76 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
VREF 鈥� 0.2
VREF + 0.2
1.5
1.485
30
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Test Point
30 pF
25
SSTL3
Class II
VTT
Table 2-77 SSTL3 Class II
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V, VREF = 1.5 V
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.66
2.07
0.04
1.25
0.43
2.10
1.67
4.34
3.91
ns
鈥�1
0.56
1.76
0.04
1.06
0.36
1.79
1.42
3.69
3.32
ns
鈥�2
0.49
1.54
0.03
0.93
0.32
1.57
1.25
3.24
2.92
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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