Revision 13 2-19 Table 2-17 Summary of I/O Timing Characteristics鈥擲oftware Default Settings " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A3PE3000-FGG324I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 90/162闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 3M 324-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 84
绯诲垪锛� ProASIC3E
RAM 浣嶇附瑷堬細 516096
杓稿叆/杓稿嚭鏁�(sh霉)锛� 221
闁€鏁�(sh霉)锛� 3000000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 324-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 324-FBGA锛�19x19锛�
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�鐣�(d膩ng)鍓嶇90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�绗�143闋�绗�144闋�绗�145闋�绗�146闋�绗�147闋�绗�148闋�绗�149闋�绗�150闋�绗�151闋�绗�152闋�绗�153闋�绗�154闋�绗�155闋�绗�156闋�绗�157闋�绗�158闋�绗�159闋�绗�160闋�绗�161闋�绗�162闋�
ProASIC3E Flash Family FPGAs
Revision 13
2-19
Table 2-17 Summary of I/O Timing Characteristics鈥擲oftware Default Settings
鈥�2 Speed Grade, Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V
I/O Standard
Drive
Strength
(mA)
Equivalent
Software
Default
Drive
Strength
Option)1
Slew
Rate
Cap
acitiv
eLo
ad
(pF
)
Extern
al
Resisto
r(
)
t DOU
T(ns)
t DP
(ns)
t DIN
(n
s)
t PY
(ns)
t PY
S
(ns)
t EOU
T
(ns)
t ZL
(ns)
t ZH
(ns)
t LZ
(ns)
t HZ
(ns)
t ZLS
(n
s)
t ZHS
(ns)
3.3 V LVTTL /
3.3 V LVCMOS
12
High 35
鈥�
0.49 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46 3.81
3.3 V LVCMOS
Wide Range2
100 A
12
High 35
鈥�
0.49 4.24 0.03 1.36 1.78 0.32 4.24 3.25 3.78 4.17 6.77 5.79
2.5 V LVCMOS
12
High 35
鈥�
0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28
1.8 V LVCMOS
12
High 35
鈥�
0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98
1.5 V LVCMOS
12
High 35
鈥�
0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37
3.3 V PCI
Per PCI
spec
鈥�
High 10
25 3 0.49 2.09 0.03 0.78 1.17 0.32 2.13 1.49 2.45 2.70 3.80 3.16
3.3 V PCI-X
Per PCI-X
spec
鈥�
High 10
253 0.49 2.09 0.03 0.78 1.17 0.32 2.13 1.49 2.45 2.70 3.80 3.16
3.3 V GTL
20 4
鈥�
High 10
25 0.45 1.55 0.03 2.19 鈥� 0.32 1.52 1.55 鈥�
鈥� 3.19 3.22
2.5 V GTL
20 4
鈥�
High 10
25 0.45 1.59 0.03 1.83 鈥� 0.32 1.61 1.59 鈥�
鈥� 3.28 3.26
3.3 V GTL+
35
鈥�
High 10
25 0.45 1.53 0.03 1.19 鈥� 0.32 1.56 1.53 鈥�
鈥� 3.23 3.20
2.5 V GTL+
33
鈥�
High 10
25 0.45 1.65 0.03 1.13 鈥� 0.32 1.68 1.57 鈥�
鈥� 3.35 3.24
HSTL (I)
8
鈥�
High 20
50 0.49 2.37 0.03 1.59 鈥� 0.32 2.42 2.35 鈥�
鈥� 4.09 4.02
HSTL (II)
15 4
鈥�
High 20
25 0.49 2.26 0.03 1.59 鈥� 0.32 2.30 2.03 鈥�
鈥� 3.97 3.70
SSTL2 (I)
15
鈥�
High 30
50 0.49 1.59 0.03 1.00 鈥� 0.32 1.62 1.38 鈥�
鈥� 3.29 3.05
SSTL2 (II)
18
鈥�
High 30
25 0.49 1.62 0.03 1.00 鈥� 0.32 1.65 1.32 鈥�
鈥� 3.32 2.99
SSTL3 (I)
14
鈥�
High 30
50 0.49 1.72 0.03 0.93 鈥� 0.32 1.75 1.37 鈥�
鈥� 3.42 3.04
SSTL3 (II)
21
鈥�
High 30
25 0.49 1.54 0.03 0.93 鈥� 0.32 1.57 1.25 鈥�
鈥� 3.24 2.92
LVDS/B-LVDS/
M-LVDS
24
鈥�
High 鈥�
鈥�
0.49 1.40 0.03 1.36 鈥�
鈥�
LVPECL
24
鈥�
High 鈥�
鈥�
0.49 1.36 0.03 1.22 鈥�
鈥�
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 卤100 A. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3V wide range as specified in the JESD8b specification.
3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-11 on page 2-37 for
connectivity. This resistor is not required during normal operation.
4. Output drive strength is below JEDEC specification.
5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5..
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