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    參數(shù)資料
    型號: A3PE3000-FGG324
    廠商: Microsemi SoC
    文件頁數(shù): 152/162頁
    文件大?。?/td> 0K
    描述: IC FPGA 1KB FLASH 3M 324-FBGA
    標(biāo)準(zhǔn)包裝: 84
    系列: ProASIC3E
    RAM 位總計(jì): 516096
    輸入/輸出數(shù): 221
    門數(shù): 3000000
    電源電壓: 1.425 V ~ 1.575 V
    安裝類型: 表面貼裝
    工作溫度: 0°C ~ 70°C
    封裝/外殼: 324-BGA
    供應(yīng)商設(shè)備封裝: 324-FBGA(19x19)
    ProASIC3E Flash Family FPGAs
    Revision 13
    1-3
    Advanced Architecture
    The proprietary ProASIC3E architecture provides granularity comparable to standard-cell ASICs. The
    ProASIC3E device consists of five distinct and programmable architectural features (Figure 1-1 on
    FPGA VersaTiles
    Dedicated FlashROM
    Dedicated SRAM/FIFO memory
    Extensive CCCs and PLLs
    Pro I/O structure
    The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic
    function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch
    interconnections. The versatility of the ProASIC3E core tile as either a three-input lookup table (LUT)
    equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile
    capability is unique to the ProASIC family of third-generation architecture Flash FPGAs. VersaTiles are
    connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the
    device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is
    possible for virtually any design.
    Figure 1-1 ProASIC3E Device Architecture Overview
    4,608-Bit Dual-Port SRAM
    or FIFO Block
    VersaTile
    RAM Block
    CCC
    Pro I/Os
    ISP AES Decryption
    User Nonvolatile
    FlashROM
    Charge Pumps
    4,608-Bit Dual-Port SRAM
    or FIFO Block
    RAM Block
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