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鏂囦欢澶у皬锛� 0K
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ProASIC3E DC and Switching Characteristics
2-20
Revision 13
Detailed I/O DC Characteristics
Table 2-18 Input Capacitance
Symbol
Definition
Conditions
Min.
Max.
Units
CIN
Input capacitance
VIN = 0, f = 1.0 MHz
8
pF
CINCLK
Input capacitance on the clock pin
VIN = 0, f = 1.0 MHz
8
pF
Table 2-19 I/O Output Buffer Maximum Resistances1
Standard
Drive Strength
RPULL-DOWN ()2
RPULL-UP ()3
3.3 V LVTTL / 3.3 V LVCMOS
4 mA
100
300
8 mA
50
150
12 mA
25
75
16 mA
17
50
24 mA
11
33
3.3 V LVCMOS Wide Range
100 A
Same as regular
3.3 V LVCMOS
Same as regular
3.3 V LVCMOS
2.5 V LVCMOS
4 mA
100
200
8 mA
50
100
12 mA
25
50
16 mA
20
40
24 mA
11
22
1.8 V LVCMOS
2 mA
200
225
4 mA
100
112
6 mA
50
56
8 mA
50
56
12 mA
20
22
16 mA
20
22
1.5 V LVCMOS
2 mA
200
224
4 mA
100
112
6 mA
67
75
8 mA
33
37
12 mA
33
37
3.3 V PCI/PCI-X
Per PCI/PCI-X
specification
25
75
3.3 V GTL
20 mA 4
11
鈥�
2.5 V GTL
20 mA 4
14
鈥�
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located on the
Microsemi SoC Products Group website at www.microsemi.com/soc/techdocs/models/ibis.html.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax 鈥� VOHspec) / IOHspec
4. Output drive strength is below JEDEC specification.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
10350-A200-60 JUNCTION SHELL 50POS
EP4CE55F29C7N IC CYCLONE IV E FPGA 56K 780FBGA
10350-A200-50 JUNCTION SHELL 50POS
XM2S-2511 CONN HOOD DSUB 25POS KIT
EP4CE55F29C8LN IC CYCLONE IV FPGA 55K 780FBGA
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