2-26 Revision 13 Summary of I/O Timing Characteristics 鈥� Default I/O Software Settings
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A3P600L-FGG144I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 180/242闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 600K 144-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 160
绯诲垪锛� ProASIC3L
RAM 浣嶇附瑷堬細 110592
杓稿叆/杓稿嚭鏁�(sh霉)锛� 97
闁€鏁�(sh霉)锛� 600000
闆绘簮闆诲锛� 1.14V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 144-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
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ProASIC3L DC and Switching Characteristics
2-26
Revision 13
Summary of I/O Timing Characteristics 鈥� Default I/O Software
Settings
Table 2-27 Summary of AC Measuring Points
Standard
Input Reference Voltage
(VREF_TYP)
Board Termination
Voltage (VTT_REF)
Measuring Trip Point
(Vtrip)
3.3 V LVTTL /
3.3 V LVCMOS
鈥�
1.4 V
3.3 V LVCMOS Wide Range
鈥�
1.4 V
2.5 V LVCMOS
鈥�
1.2 V
1.8 V LVCMOS
鈥�
0.90 V
1.5 V LVCMOS
鈥�
0.75 V
1.2 V LVCMOS *
鈥�
0.6 V
1.2 V LVCMOS Wide Range*
鈥�
0.6 V
3.3 V PCI
鈥�
0.285 * VCCI (RR)
0.615 * VCCI (FF))
3.3 V PCI-X
鈥�
0.285 * VCCI (RR)
0.615 * VCCI (FF)
3.3 V GTL
0.8 V
1.2 V
VREF
2.5 V GTL
0.8 V
1.2 V
VREF
3.3 V GTL+
1.0 V
1.5 V
VREF
2.5 V GTL+
1.0 V
1.5 V
VREF
HSTL (I)
0.75 V
VREF
HSTL (II)
0.75 V
VREF
SSTL2 (I)
1.25 V
VREF
SSTL2 (II)
1.25 V
VREF
SSTL3 (I)
1.5 V
1.485 V
VREF
SSTL3 (II)
1.5 V
1.485 V
VREF
LVDS
鈥�
Cross point
LVPECL
鈥�
Cross point
Note: *Applicable only to devices operating in the 1.2 V core range.
Table 2-28 I/O AC Parameter Definitions
Parameter
Parameter Definition
tDP
Data to Pad delay through the Output Buffer
tPY
Pad to Data delay through the Input Buffer
tDOUT
Data to Output Buffer delay through the I/O interface
tEOUT
Enable to Output Buffer Tristate Control delay through the I/O interface
tDIN
Input Buffer to Data delay through the I/O interface
tHZ
Enable to Pad delay through the Output Buffer鈥擧igh to Z
tZH
Enable to Pad delay through the Output Buffer鈥擹 to High
tLZ
Enable to Pad delay through the Output Buffer鈥擫ow to Z
tZL
Enable to Pad delay through the Output Buffer鈥擹 to Low
tZHS
Enable to Pad delay through the Output Buffer with delayed enable鈥擹 to High
tZLS
Enable to Pad delay through the Output Buffer with delayed enable鈥擹 to Low
鐩搁棞(gu膩n)PDF璩囨枡
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