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ProASIC3L DC and Switching Characteristics
2-40
Revision 13
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 100°C, the short current condition would have to be sustained for more than six months
to cause a reliability concern. The I/O design does not contain any short circuit protection, but such
protection would only be needed in extremely prolonged stress conditions.
Table 2-42 I/O Short Currents IOSH/IOSL
Applicable to Standard Plus I/O Banks
Drive Strength
IOSL (mA)*
IOSH (mA)*
3.3 V LVTTL / 3.3 V
LVCMOS
2 mA
25
27
4 mA
25
27
6 mA
51
54
8 mA
51
54
12 mA
103
109
16 mA
103
109
3.3 V LVCMOS Wide Range
100 A
Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS
2.5 V LVCMOS
2 mA
16
18
4 mA
16
18
6 mA
32
37
8 mA
32
37
12 mA
65
74
1.8 V LVCMOS
2 mA
9
11
4 mA
17
22
6 mA
35
44
8 mA
35
44
1.5 V LVCMOS
2 mA
13
16
4 mA
25
33
1.2 V LVCMOS
2 mA
20
26
1.2 V LVCMOS Wide Range
100 A
20
26
3.3 V PCI/PCI-X
Per PCI/PCI-X
specification
103
109
Note: TJ = 100°C
Table 2-43 Schmitt Trigger Input Hysteresis, Hysteresis Voltage Value (Typ) for Schmitt Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (typ.)
3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode)
240 mV
2.5 V LVCMOS (Schmitt trigger mode)
140 mV
1.8 V LVCMOS (Schmitt trigger mode)
80 mV
1.5 V LVCMOS (Schmitt trigger mode)
60 mV
1.2 V LVCMOS (Schmitt trigger mode)
40 mV