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鍨嬭櫉(h脿o)锛� A3P600L-FG484
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 41/242闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 600K 484-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 40
绯诲垪锛� ProASIC3L
RAM 浣嶇附瑷�(j矛)锛� 110592
杓稿叆/杓稿嚭鏁�(sh霉)锛� 235
闁€鏁�(sh霉)锛� 600000
闆绘簮闆诲锛� 1.14V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 484-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 484-FPBGA锛�23x23锛�
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ProASIC3L Low Power Flash FPGAs
Revision 13
2-119
Timing Characteristics
1.5 V DC Core Voltage
Figure 2-34 Output DDR Timing Diagram
11
6
1
7
2
8
3
910
45
28
3
9
tDDROREMCLR
tDDROHD1
tDDROREMCLR
tDDROHD2
tDDROSUD2
tDDROCLKQ
tDDRORECCLR
CLK
Data_R
Data_F
CLR
Out
tDDROCLR2Q
710
4
Table 2-198 Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
鈥�1
Std.
Units
tDDROCLKQ
Clock-to-Out of DDR for Output DDR
0.72
0.84
ns
tDDRISUD1
Data_F Data Setup for Output DDR
0.39
0.45
ns
tDDROSUD2
Data_R Data Setup for Output DDR
0.39
0.45
ns
tDDROHD1
Data_F Data Hold for Output DDR
0.00
ns
tDDROHD2
Data_R Data Hold for Output DDR
0.00
ns
tDDROCLR2Q
Asynchronous Clear-to-Out for Output DDR
0.82
0.96
ns
tDDROREMCLR
Asynchronous Clear Removal Time for Output DDR
0.00
ns
tDDRORECCLR
Asynchronous Clear Recovery Time for Output DDR
0.23
0.27
ns
tDDROWCLR1
Asynchronous Clear Minimum Pulse Width for Output DDR
0.19
0.22
ns
tDDROCKMPWH
Clock Minimum Pulse Width High for the Output DDR
0.31
0.36
ns
tDDROCKMPWL
Clock Minimum Pulse Width Low for the Output DDR
0.28
0.32
ns
FDDOMAX
Maximum Frequency for the Output DDR
250.00 250.00
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
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