2-94 Revision 13 Timing Characteristics Figure 2-34 RAM Reset. Applicable to Both RAM4K9 " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A3P600-2FGG256I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 11/220闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 600K 256-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� ProASIC3
RAM 浣嶇附瑷�(j矛)锛� 110592
杓稿叆/杓稿嚭鏁�(sh霉)锛� 177
闁€鏁�(sh霉)锛� 600000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 256-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 256-FPBGA锛�17x17锛�
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�鐣�(d膩ng)鍓嶇11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�绗�143闋�绗�144闋�绗�145闋�绗�146闋�绗�147闋�绗�148闋�绗�149闋�绗�150闋�绗�151闋�绗�152闋�绗�153闋�绗�154闋�绗�155闋�绗�156闋�绗�157闋�绗�158闋�绗�159闋�绗�160闋�绗�161闋�绗�162闋�绗�163闋�绗�164闋�绗�165闋�绗�166闋�绗�167闋�绗�168闋�绗�169闋�绗�170闋�绗�171闋�绗�172闋�绗�173闋�绗�174闋�绗�175闋�绗�176闋�绗�177闋�绗�178闋�绗�179闋�绗�180闋�绗�181闋�绗�182闋�绗�183闋�绗�184闋�绗�185闋�绗�186闋�绗�187闋�绗�188闋�绗�189闋�绗�190闋�绗�191闋�绗�192闋�绗�193闋�绗�194闋�绗�195闋�绗�196闋�绗�197闋�绗�198闋�绗�199闋�绗�200闋�绗�201闋�绗�202闋�绗�203闋�绗�204闋�绗�205闋�绗�206闋�绗�207闋�绗�208闋�绗�209闋�绗�210闋�绗�211闋�绗�212闋�绗�213闋�绗�214闋�绗�215闋�绗�216闋�绗�217闋�绗�218闋�绗�219闋�绗�220闋�
ProASIC3 DC and Switching Characteristics
2-94
Revision 13
Timing Characteristics
Figure 2-34 RAM Reset. Applicable to Both RAM4K9 and RAM512x18.
CLK
RESET
DOUT|RD
Dn
tCYC
tCKH
tCKL
tRSTBQ
Dm
Table 2-116 RAM4K9
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
鈥�2
鈥�1
Std. Units
tAS
Address setup time
0.25 0.28 0.33
ns
tAH
Address hold time
0.00 0.00 0.00
ns
tENS
REN, WEN setup time
0.14 0.16 0.19
ns
tENH
REN, WEN hold time
0.10 0.11 0.13
ns
tBKS
BLK setup time
0.23 0.27 0.31
ns
tBKH
BLK hold time
0.02 0.02 0.02
ns
tDS
Input data (DIN) setup time
0.18 0.21 0.25
ns
tDH
Input data (DIN) hold time
0.00 0.00 0.00
ns
tCKQ1
Clock High to new data valid on DOUT (output retained, WMODE = 0)
2.36 2.68 3.15
ns
Clock High to new data valid on DOUT (flow-through, WMODE = 1)
1.79 2.03 2.39
ns
tCKQ2
Clock High to new data valid on DOUT (pipelined)
0.89 1.02 1.20
ns
tC2CWWL1
Address collision clk-to-clk delay for reliable write after write on same
address鈥擜pplicable to Closing Edge
0.33 0.28 0.25
ns
tC2CWWH1
Address collision clk-to-clk delay for reliable write after write on same
address鈥擜pplicable to Rising Edge
0.30 0.26 0.23
ns
tC2CRWH1
Address collision clk-to-clk delay for reliable read access after write on same
address鈥擜pplicable to Opening Edge
0.45 0.38 0.34
ns
tC2CWRH1
Address collision clk-to-clk delay for reliable write access after read on same
address鈥� Applicable to Opening Edge
0.49 0.42 0.37
ns
tRSTBQ
RESET Low to data out Low on DOUT (flow-through)
0.92 1.05 1.23
ns
RESET Low to Data Out Low on DOUT (pipelined)
0.92 1.05 1.23
ns
tREMRSTB
RESET removal
0.29 0.33 0.38
ns
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
RMC44DRAH-S734 CONN EDGECARD 88POS .100 R/A PCB
IDT71V424S12PHGI IC SRAM 4MBIT 12NS 44TSOP
A3P600-2FG256I IC FPGA 1KB FLASH 600K 256-FBGA
IDT71V416S10BEG IC SRAM 4MBIT 10NS 48FBGA
M1A3P600-2FGG256I IC FPGA 1KB FLASH 600K 256-FBGA
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
A3P600-2FGG484 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 600K 484-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:ProASIC3 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
A3P600-2FGG484I 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 600K 484-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:ProASIC3 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A3P600-2PQ144 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs
A3P600-2PQ144ES 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs
A3P600-2PQ144I 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs