2-12 Revision 13 Total Dynamic Power Consumption鈥擯DYN
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A3P600-1FGG144I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 140/220闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 600K 144-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 160
绯诲垪锛� ProASIC3
RAM 浣嶇附瑷�(j矛)锛� 110592
杓稿叆/杓稿嚭鏁�(sh霉)锛� 97
闁€鏁�(sh霉)锛� 600000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 144-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
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ProASIC3 DC and Switching Characteristics
2-12
Revision 13
Total Dynamic Power Consumption鈥擯DYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution鈥擯CLOCK
PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK
NSPINE is the number of global spines used in the user design鈥攇uidelines are provided in the
"Spine Architecture" section of the Global Resources chapter in the ProASIC3 FPGA
NROW is the number of VersaTile rows used in the design鈥攇uidelines are provided in the "Spine
Architecture" section of the Global Resources chapter in the ProASIC3 FPGA Fabric
FCLK is the global clock signal frequency.
NS-CELL is the number of VersaTiles used as sequential modules in the design.
PAC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution鈥擯S-CELL
PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile
sequential cell is used, it should be accounted for as 1.
1 is the toggle rate of VersaTile outputs鈥攇uidelines are provided in Table 2-16 on page 2-13.
FCLK is the global clock signal frequency.
Combinatorial Cells Contribution鈥擯C-CELL
PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs鈥攇uidelines are provided in Table 2-16 on page 2-13.
FCLK is the global clock signal frequency.
Routing Net Contribution鈥擯NET
PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs鈥攇uidelines are provided in Table 2-16 on page 2-13.
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution鈥擯INPUTS
PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
2 is the I/O buffer toggle rate鈥攇uidelines are provided in Table 2-16 on page 2-13.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution鈥擯OUTPUTS
POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
2 is the I/O buffer toggle rate鈥攇uidelines are provided in Table 2-16 on page 2-13.
1 is the I/O buffer enable rate鈥攇uidelines are provided in Table 2-17 on page 2-13.
FCLK is the global clock signal frequency.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
M1A3P600-1FGG144I IC FPGA 1KB FLASH 600K 144-FBGA
A3P600-1FG144I IC FPGA 1KB FLASH 600K 144-FBGA
RSC43DRST-S273 CONN EDGECARD 86POS DIP .100 SLD
RSM43DTMT-S189 CONN EDGECARD 86POS R/A .156 SLD
RMM43DTMT-S189 CONN EDGECARD 86POS R/A .156 SLD
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
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