Revision 13 2-87 Table 2-111 A3P250 Global Resource Commercial-Case Conditions: T
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A3P600-1FGG144
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 4/220闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 600K 144-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 160
绯诲垪锛� ProASIC3
RAM 浣嶇附瑷�(j矛)锛� 110592
杓稿叆/杓稿嚭鏁�(sh霉)锛� 97
闁€鏁�(sh霉)锛� 600000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 144-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
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ProASIC3 Flash Family FPGAs
Revision 13
2-87
Table 2-111 A3P250 Global Resource
Commercial-Case Conditions: TJ = 70掳C, VCC = 1.425 V
Parameter
Description
鈥�2
鈥�1
Std.
Units
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2
tRCKL
Input Low Delay for Global Clock
0.80
1.01
0.91
1.15
1.07
1.36
ns
tRCKH
Input High Delay for Global Clock
0.78
1.04
0.89
1.18
1.04
1.39
ns
tRCKMPWH Minimum Pulse Width High for Global Clock
0.75
0.85
1.00
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
0.85
0.96
1.13
ns
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-112 A3P400 Global Resource
Commercial-Case Conditions: TJ = 70掳C, VCC = 1.425 V
Parameter
Description
鈥�2
鈥�1
Std.
Units
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2
tRCKL
Input Low Delay for Global Clock
0.871.090.991.241.171.46
ns
tRCKH
Input High Delay for Global Clock
0.86
1.11
0.98
1.27
1.15
1.49
ns
tRCKMPWH Minimum Pulse Width High for Global Clock
0.75
0.85
1.00
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
0.85
0.96
1.13
ns
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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A3P600-1FGG256 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 600K 256-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
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