Revision 13 2-23 Table 2-25 Summary of I/O Timing Characteristics鈥擲oftware Default Settings 鈥�" />
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鍨嬭櫉锛� A3P400-FG256I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 152/220闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 400K 256-FBGA
妯欐簴鍖呰锛� 90
绯诲垪锛� ProASIC3
RAM 浣嶇附瑷堬細 55296
杓稿叆/杓稿嚭鏁�(sh霉)锛� 178
闁€鏁�(sh霉)锛� 400000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 256-LBGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 256-FPBGA锛�17x17锛�
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ProASIC3 Flash Family FPGAs
Revision 13
2-23
Table 2-25 Summary of I/O Timing Characteristics鈥擲oftware Default Settings
鈥�2 Speed Grade, Commercial-Case Conditions: TJ = 70掳C, Worst Case VCC = 1.425 V,
Worst-Case VCCI (per standard)
Standard Plus I/O Banks
I/O Standard
D
rive
S
tre
ng
th
Equiv
.Sof
tware
Default
Dri
v
eS
tre
ng
th
Opt
ion
1
Slew
Rate
C
ap
a
citive
L
o
a
d
(pF
)
Ex
tern
al
Re
sistor
t DO
UT
(ns)
t DP
(ns)
t DI
N
(ns)
t PY
(ns)
t EOUT
(ns)
t ZL
(ns)
t ZH
(ns)
t LZ
(ns)
t HZ
(ns)
t ZL
S
(ns)
t ZH
S
(n
s)
Un
it
s
3.3 V LVTTL /
3.3 V LVCMOS
12 mA 12 mA High 35
鈥� 0.45 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60 ns
3.3 V LVCMOS
Wide Range2
100 A 12 mA High 35
鈥� 0.45 3.65 0.03 1.14 0.32 3.65 2.93 3.22 3.72 6.18 5.46 ns
2.5 V LVCMOS 12 mA 12 mA High 35
鈥� 0.45 2.39 0.03 0.97 0.32 2.44 2.35 2.11 2.32 4.11 4.02 ns
1.8 V LVCMOS
8 mA 8 mA High 35
鈥� 0.45 3.03 0.03 0.90 0.32 2.87 3.03 2.19 2.32 4.54 4.70 ns
1.5 V LVCMOS
4 mA 4 mA High 35
鈥� 0.45 3.61 0.03 1.06 0.32 3.35 3.61 2.26 2.34 5.02 5.28 ns
3.3 V PCI
Per
PCI
spec
鈥�
High 10 25 4 0.45 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns
3.3 V PCI-X
Per
PCI-X
spec
鈥�
High 10 25 4 0.45 1.72 0.03 0.62 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 卤100 A. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-63 for
connectivity. This resistor is not required during normal operation.
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