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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | A3P250L-FGG144 |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋佹暩(sh霉)锛� | 31/242闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FPGA 1KB FLASH 250K 144-FBGA |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 160 |
| 绯诲垪锛� | ProASIC3L |
| RAM 浣嶇附瑷�(j矛)锛� | 36864 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 97 |
| 闁€鏁�(sh霉)锛� | 250000 |
| 闆绘簮闆诲锛� | 1.14V ~ 1.575 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 144-LBGA |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 144-FPBGA锛�13x13锛� |
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ProASIC3L DC and Switching Characteristics
2-110
Revision 13
Timing Characteristics
1.5 V DC Core Voltage
1.2 V DC Core Voltage
Table 2-188 Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
鈥�1 Std. Units
tICLKQ
Clock-to-Q of the Input Data Register
0.24 0.29
ns
tISUD
Data Setup Time for the Input Data Register
0.27 0.31
ns
tIHD
Data Hold Time for the Input Data Register
0.00 0.00
ns
tISUE
Enable Setup Time for the Input Data Register
0.38 0.45
ns
tIHE
Enable Hold Time for the Input Data Register
0.00 0.00
ns
tICLR2Q
Asynchronous Clear-to-Q of the Input Data Register
0.46 0.54
ns
tIPRE2Q
Asynchronous Preset-to-Q of the Input Data Register
0.46 0.54
ns
tIREMCLR
Asynchronous Clear Removal Time for the Input Data Register
0.00 0.00
ns
tIRECCLR
Asynchronous Clear Recovery Time for the Input Data Register
0.23 0.27
ns
tIREMPRE
Asynchronous Preset Removal Time for the Input Data Register
0.00 0.00
ns
tIRECPRE
Asynchronous Preset Recovery Time for the Input Data Register
0.23 0.27
ns
tIWCLR
Asynchronous Clear Minimum Pulse Width for the Input Data Register
0.19 0.22
ns
tIWPRE
Asynchronous Preset Minimum Pulse Width for the Input Data Register
0.19 0.22
ns
tICKMPWH
Clock Minimum Pulse Width High for the Input Data Register
0.31 0.36
ns
tICKMPWL
Clock Minimum Pulse Width Low for the Input Data Register
0.28 0.32
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-189 Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.14 V
Parameter
Description
鈥�1 Std. Units
tICLKQ
Clock-to-Q of the Input Data Register
0.32 0.37
ns
tISUD
Data Setup Time for the Input Data Register
0.35 0.41
ns
tIHD
Data Hold Time for the Input Data Register
0.00 0.00
ns
tISUE
Enable Setup Time for the Input Data Register
0.50 0.58
ns
tIHE
Enable Hold Time for the Input Data Register
0.00 0.00
ns
tICLR2Q
Asynchronous Clear-to-Q of the Input Data Register
0.60 0.71
ns
tIPRE2Q
Asynchronous Preset-to-Q of the Input Data Register
0.60 0.71
ns
tIREMCLR
Asynchronous Clear Removal Time for the Input Data Register
0.00 0.00
ns
tIRECCLR
Asynchronous Clear Recovery Time for the Input Data Register
0.30 0.35
ns
tIREMPRE
Asynchronous Preset Removal Time for the Input Data Register
0.00 0.00
ns
tIRECPRE
Asynchronous Preset Recovery Time for the Input Data Register
0.30 0.35
ns
tIWCLR
Asynchronous Clear Minimum Pulse Width for the Input Data Register
0.19 0.22
ns
tIWPRE
Asynchronous Preset Minimum Pulse Width for the Input Data Register
0.19 0.22
ns
tICKMPWH
Clock Minimum Pulse Width High for the Input Data Register
0.31 0.36
ns
tICKMPWL
Clock Minimum Pulse Width Low for the Input Data Register
0.28 0.32
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| RMA50DRMS | CONN EDGECARD 100POS .125 SQ WW |
| A3P250L-FG144 | IC FPGA 1KB FLASH 250K 144-FBGA |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| A3P250L-FGG144I | 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 250K 144-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:ProASIC3L 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛� |
| A3P250L-FGG256 | 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 250K 256-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:ProASIC3L 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛� |
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| A3P250L-PQ208I | 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 250K 208-PQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:ProASIC3L 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛� |
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