2-112 Revision 13 Timing Characteristics 1.5 V DC Core Voltage 1.2 V DC Core Voltage T" />
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鍨嬭櫉(h脿o)锛� A3P250L-FG144I
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 33/242闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 250K 144-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 160
绯诲垪锛� ProASIC3L
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 97
闁€(m茅n)鏁�(sh霉)锛� 250000
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瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 144-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
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ProASIC3L DC and Switching Characteristics
2-112
Revision 13
Timing Characteristics
1.5 V DC Core Voltage
1.2 V DC Core Voltage
Table 2-190 Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
鈥�1
Std. Units
tOCLKQ
Clock-to-Q of the Output Data Register
0.60 0.71
ns
tOSUD
Data Setup Time for the Output Data Register
0.32 0.37
ns
tOHD
Data Hold Time for the Output Data Register
0.00 0.00
ns
tOSUE
Enable Setup Time for the Output Data Register
0.45 0.53
ns
tOHE
Enable Hold Time for the Output Data Register
0.00 0.00
ns
tOCLR2Q
Asynchronous Clear-to-Q of the Output Data Register
0.82 0.96
ns
tOPRE2Q
Asynchronous Preset-to-Q of the Output Data Register
0.82 0.96
ns
tOREMCLR
Asynchronous Clear Removal Time for the Output Data Register
0.00 0.00
ns
tORECCLR
Asynchronous Clear Recovery Time for the Output Data Register
0.23 0.27
ns
tOREMPRE
Asynchronous Preset Removal Time for the Output Data Register
0.00 0.00
ns
tORECPRE
Asynchronous Preset Recovery Time for the Output Data Register
0.23 0.27
ns
tOWCLR
Asynchronous Clear Minimum Pulse Width for the Output Data Register
0.19 0.22
ns
tOWPRE
Asynchronous Preset Minimum Pulse Width for the Output Data Register
0.19 0.22
ns
tOCKMPWH
Clock Minimum Pulse Width High for the Output Data Register
0.31 0.36
ns
tOCKMPWL
Clock Minimum Pulse Width Low for the Output Data Register
0.28 0.32
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-191 Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.14 V
Parameter
Description
鈥�1
Std. Units
tOCLKQ
Clock-to-Q of the Output Data Register
0.78 0.92
ns
tOSUD
Data Setup Time for the Output Data Register
0.42 0.49
ns
tOHD
Data Hold Time for the Output Data Register
0.00 0.00
ns
tOSUE
Enable Setup Time for the Output Data Register
0.58 0.69
ns
tOHE
Enable Hold Time for the Output Data Register
0.00 0.00
ns
tOCLR2Q
Asynchronous Clear-to-Q of the Output Data Register
1.07 1.26
ns
tOPRE2Q
Asynchronous Preset-to-Q of the Output Data Register
1.07 1.26
ns
tOREMCLR
Asynchronous Clear Removal Time for the Output Data Register
0.00 0.00
ns
tORECCLR
Asynchronous Clear Recovery Time for the Output Data Register
0.30 0.35
ns
tOREMPRE
Asynchronous Preset Removal Time for the Output Data Register
0.00 0.00
ns
tORECPRE
Asynchronous Preset Recovery Time for the Output Data Register
0.30 0.35
ns
tOWCLR
Asynchronous Clear Minimum Pulse Width for the Output Data Register
0.19 0.22
ns
tOWPRE
Asynchronous Preset Minimum Pulse Width for the Output Data Register
0.19 0.22
ns
tOCKMPWH
Clock Minimum Pulse Width High for the Output Data Register
0.31 0.36
ns
tOCKMPWL
Clock Minimum Pulse Width Low for the Output Data Register
0.28 0.32
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
鐩搁棞(gu膩n)PDF璩囨枡
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