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ProASIC3 Flash Family FPGAs
Revision 13
2-25
Detailed I/O DC Characteristics
Table 2-27 Input Capacitance
Symbol
Definition
Conditions
Min.
Max.
Units
CIN
Input capacitance
VIN = 0, f = 1.0 MHz
8
pF
CINCLK
Input capacitance on the clock pin
VIN = 0, f = 1.0 MHz
8
pF
Table 2-28 I/O Output Buffer Maximum Resistances1
Applicable to Advanced I/O Banks
Standard
Drive Strength
RPULL-DOWN ()2
RPULL-UP ()3
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
100
300
4 mA
100
300
6 mA
50
150
8 mA
50
150
12 mA
25
75
16 mA
17
50
24 mA
11
33
3.3 V LVCMOS Wide Range4
100 A
Same as regular
3.3 V LVCMOS
Same as regular
3.3 V LVCMOS
2.5 V LVCMOS
2 mA
100
200
4 mA
100
200
6 mA
50
100
8 mA
50
100
12 mA
25
50
16 mA
20
40
24 mA
11
22
1.8 V LVCMOS
2 mA
200
225
4 mA
100
112
6 mA
50
56
8 mA
50
56
12 mA
20
22
16 mA
20
22
1.5 V LVCMOS
2 mA
200
224
4 mA
100
112
6 mA
67
75
8 mA
33
37
12 mA
33
37
3.3 V PCI/PCI-X
Per PCI/PCI-X
specification
25
75
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located at
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax 鈥� VOHspec) / IOHspec
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B
specification.
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