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寤犲晢锛� Microsemi SoC
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绯诲垪锛� ProASIC3
RAM 浣嶇附瑷堬細 36864
杓稿叆/杓稿嚭鏁革細 97
闁€鏁革細 250000
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瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
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ProASIC3 Flash Family FPGAs
Revision 13
1-7
I/Os with Advanced I/O Standards
The ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V,
1.8 V, 2.5 V, and 3.3 V). ProASIC3 FPGAs support many different I/O standards鈥攕ingle-ended and
differential.
The I/Os are organized into banks, with two or four banks per device. The configuration of these banks
determines the I/O standards supported (Table 1-1).
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
Single-Data-Rate applications
Double-Data-Rate applications鈥擠DR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications
ProASIC3 banks for the A3P250 device and above support LVPECL, LVDS, B-LVDS and M-LVDS.
B-LVDS and M-LVDS can support up to 20 loads.
Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card
in a powered-up system.
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed
when the system is powered up, while the component itself is powered down, or when power supplies
are floating.
Wide Range I/O Support
ProASIC3 devices support JEDEC-defined wide range I/O operation. ProASIC3 supports the JESD8-B
specification, covering both 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V.
Wider I/O range means designers can eliminate power supplies or power conditioning components from
the board or move to less costly components with greater tolerances. Wide range eases I/O bank
management and provides enhanced protection from system voltage spikes, while providing the flexibility
to easily run custom voltage applications.
Specifying I/O States During Programming
You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for
PDB files generated from Designer v8.5 or greater. See the FlashPro User鈥檚 Guide for more information.
Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have
limited display of Pin Numbers only.
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during
programming.
2. From the FlashPro GUI, click PDB Configuration. A FlashPoint 鈥� Programming File Generator
window appears.
3. Click the Specify I/O States During Programming button to display the Specify I/O States During
Programming dialog box.
Table 1-1 I/O Standards Supported
I/O Bank Type
Device and Bank Location
I/O Standards Supported
LVTTL/
LVCMOS PCI/PCI-X
LVPECL, LVDS,
B-LVDS, M-LVDS
Advanced
East and west Banks of A3P250 and
larger devices
Standard Plus
North and south banks of A3P250 and
larger devices
All banks of A3P060 and A3P125
Not supported
Standard
All banks of A3P015 and A3P030
Not
supported
Not supported
鐩搁棞PDF璩囨枡
PDF鎻忚堪
A3P250-2FGG144I IC FPGA 1KB FLASH 250K 144-FBGA
M1A3P250-2FGG144I IC FPGA 1KB FLASH 250K 144-FBGA
M1A3P250-2FG144I IC FPGA 1KB FLASH 250K 144-FBGA
AGLP125V2-CS281 IC FPGA IGLOO PLUS 125K 281-CSP
AGLP125V2-CSG281 IC FPGA IGLOO PLUS 125K 281-CSP
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