Revision 13 2-75 Timing Characteristics Table 2-100 Output Enable Register Propagation Delays
鍙冩暩璩囨枡
鍨嬭櫉锛� A3P125-TQ144I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩锛� 209/220闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 125K 144-TQFP
妯欐簴鍖呰锛� 60
绯诲垪锛� ProASIC3
RAM 浣嶇附瑷堬細 36864
杓稿叆/杓稿嚭鏁革細 100
闁€鏁革細 125000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 144-LQFP
渚涙噳鍟嗚ō鍌欏皝瑁濓細 144-TQFP锛�20x20锛�
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�绗�143闋�绗�144闋�绗�145闋�绗�146闋�绗�147闋�绗�148闋�绗�149闋�绗�150闋�绗�151闋�绗�152闋�绗�153闋�绗�154闋�绗�155闋�绗�156闋�绗�157闋�绗�158闋�绗�159闋�绗�160闋�绗�161闋�绗�162闋�绗�163闋�绗�164闋�绗�165闋�绗�166闋�绗�167闋�绗�168闋�绗�169闋�绗�170闋�绗�171闋�绗�172闋�绗�173闋�绗�174闋�绗�175闋�绗�176闋�绗�177闋�绗�178闋�绗�179闋�绗�180闋�绗�181闋�绗�182闋�绗�183闋�绗�184闋�绗�185闋�绗�186闋�绗�187闋�绗�188闋�绗�189闋�绗�190闋�绗�191闋�绗�192闋�绗�193闋�绗�194闋�绗�195闋�绗�196闋�绗�197闋�绗�198闋�绗�199闋�绗�200闋�绗�201闋�绗�202闋�绗�203闋�绗�204闋�绗�205闋�绗�206闋�绗�207闋�绗�208闋�鐣跺墠绗�209闋�绗�210闋�绗�211闋�绗�212闋�绗�213闋�绗�214闋�绗�215闋�绗�216闋�绗�217闋�绗�218闋�绗�219闋�绗�220闋�
ProASIC3 Flash Family FPGAs
Revision 13
2-75
Timing Characteristics
Table 2-100 Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
鈥�2
鈥�1
Std. Units
tOECLKQ
Clock-to-Q of the Output Enable Register
0.59 0.67 0.79
ns
tOESUD
Data Setup Time for the Output Enable Register
0.31 0.36 0.42
ns
tOEHD
Data Hold Time for the Output Enable Register
0.00 0.00 0.00
ns
tOESUE
Enable Setup Time for the Output Enable Register
0.44 0.50 0.58
ns
tOEHE
Enable Hold Time for the Output Enable Register
0.00 0.00 0.00
ns
tOECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register
0.67 0.76 0.89
ns
tOEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register
0.67 0.76 0.89
ns
tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register
0.00 0.00 0.00
ns
tOERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register
0.22 0.25 0.30
ns
tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register
0.00 0.00 0.00
ns
tOERECPRE
Asynchronous Preset Recovery Time for the Output Enable Register
0.22 0.25 0.30
ns
tOEWCLR
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
0.22 0.25 0.30
ns
tOEWPRE
Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30
ns
tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register
0.36 0.41 0.48
ns
tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register
0.32 0.37 0.43
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
鐩搁棞PDF璩囨枡
PDF鎻忚堪
A3P060-1TQ144I IC FPGA 1KB FLASH 60K 144-TQFP
A3P060-1TQG144I IC FPGA 1KB FLASH 60K 144-TQFP
EP1C3T100A8N IC CYCLONE FPGA 2910 LE 100-TQFP
AGLN250V2-CSG81I IC FPGA NANO 1KB 250K 81-CSP
BR93L76RFVT-WE2 IC EEPROM 8KBIT 2MHZ 8TSSOP
鐩搁棞浠g悊鍟�/鎶€琛撳弮鏁�
鍙冩暩鎻忚堪
A3P125-TQG144 鍔熻兘鎻忚堪:IC FPGA 1024MAC 133I/O 144TQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 妯欐簴鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�:- 閭忚集鍏冧欢/鍠厓鏁�:792 RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�:120 闁€鏁�:30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:289-CSP锛�14x14锛�
A3P125-TQG144I 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 125K 144-TQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 妯欐簴鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�:- 閭忚集鍏冧欢/鍠厓鏁�:792 RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�:120 闁€鏁�:30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:289-CSP锛�14x14锛�
A3P125-VQ100 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 125K 100-VQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 妯欐簴鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�:- 閭忚集鍏冧欢/鍠厓鏁�:792 RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�:120 闁€鏁�:30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:289-CSP锛�14x14锛�
A3P125-VQ100I 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 125K 100-VQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 妯欐簴鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�:- 閭忚集鍏冧欢/鍠厓鏁�:792 RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�:120 闁€鏁�:30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:289-CSP锛�14x14锛�
A3P125-VQ100T 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 125K 100-VQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 妯欐簴鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�:- 閭忚集鍏冧欢/鍠厓鏁�:792 RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�:120 闁€鏁�:30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:289-CSP锛�14x14锛�