Revision 13 2-9 Table 2-13 Summary of I/O Output Buffer Power (Per Pin) 鈥� Default I/O Softwar" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A3P125-1QNG132I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 137/220闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 125K 132-QFN
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
绯诲垪锛� ProASIC3
RAM 浣嶇附瑷堬細 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 84
闁€鏁�(sh霉)锛� 125000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 132-WFQFN
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 132-QFN锛�8x8锛�
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ProASIC3 Flash Family FPGAs
Revision 13
2-9
Table 2-13 Summary of I/O Output Buffer Power (Per Pin) 鈥� Default I/O Software Settings 1
Applicable to Standard I/O Banks
CLOAD (pF)
VCCI (V)
Static Power
PDC3 (mW) 2
Dynamic Power
PAC10 (W/MHz) 3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
35
3.3
鈥�
431.08
3.3 V LVCMOS Wide Range4
35
3.3
鈥�
431.08
2.5 V LVCMOS
35
2.5
鈥�
247.36
1.8 V LVCMOS
35
1.8
鈥�
128.46
1.5 V LVCMOS (JESD8-11)
35
1.5
鈥�
89.46
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC3 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCC and VCCI.
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
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A3P125-1QNG132T 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 125K 132-QFN RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
A3P125-1TQ144 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 125K 144-TQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛�
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