Revision 13 2-27 1.5 V DC Core Voltage Table 2-29 Summary of I/O Timing Characteristics鈥擲oftware De" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A3P1000L-FGG144I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 181/242闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 1M 144-FBGA
妯欐簴鍖呰锛� 160
绯诲垪锛� ProASIC3L
RAM 浣嶇附瑷堬細 147456
杓稿叆/杓稿嚭鏁�(sh霉)锛� 97
闁€鏁�(sh霉)锛� 1000000
闆绘簮闆诲锛� 1.14V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 144-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
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ProASIC3L Low Power Flash FPGAs
Revision 13
2-27
1.5 V DC Core Voltage
Table 2-29 Summary of I/O Timing Characteristics鈥擲oftware Default Settings
鈥�1 Speed Grade, Commercial-Case Conditions: TJ = 70掳C, Worst Case VCC = 1.425V,
Worst Case VCCI
Pro I/O Banks
Standard
D
rive
S
tre
ng
th
(mA)
Equiv
.S
o
ft
ware
Default
D
rive
S
tre
ng
th
Op
tio
n
1
Slew
Rate
Ca
p
aci
tiv
e
Lo
ad
(p
F)
Ex
tern
al
Re
sistor
(
)
t DO
U
T
(ns)
t DP
(ns)
t DI
N
(ns)
t PY
(ns)
t PYS
(ns)
tE
O
U
T
(ns)
t ZL
(ns)
t ZH
(ns)
t LZ
(ns)
t HZ
(ns)
t ZL
S
(ns)
t ZH
S
(n
s)
Un
it
s
3.3 V LVTTL /
3.3 V LVCMOS
12 mA 12 mA High 5
鈥� 0.50 1.89 0.03 1.34 1.85 0.33 1.93 1.42 2.51 2.77 3.64 3.13 ns
3.3 V LVCMOS
Wide Range1,2
100 A 12 mA High 5
鈥�
ns
2.5 V LVCMOS 12 mA 12 mA High 5
鈥� 0.50 1.92 0.03 1.58 1.97 0.33 1.96 1.59 2.58 2.68 3.67 3.30 ns
1.8 V LVCMOS 12 mA 12 mA High 5
鈥� 0.50 2.14 0.03 1.53 2.17 0.33 2.18 1.76 2.86 3.24 3.89 3.47 ns
1.5 V LVCMOS 12 mA 12 mA High 5
鈥� 0.50 2.46 0.03 1.69 2.36 0.33 2.51 2.04 3.03 3.35 4.22 3.75 ns
3.3 V PCI
Per
PCI
spec.
鈥�
High 5 253 0.50 2.15 0.03 2.10 2.84 0.33 2.19 1.53 2.51 2.77 3.90 3.24 ns
3.3 V PCI-X
Per
PCI-X
spec.
鈥�
High 10 253 0.50 2.15 0.03 2.10 2.84 0.33 2.19 1.53 2.51 2.77 3.90 3.24 ns
3.3 V GTL
20 mA5 20 mA5 High 10 25 0.50 1.59 0.03 1.80
鈥�
0.33 1.56 1.59
鈥�
3.27 3.30 ns
2.5 V GTL
20 mA5 20 mA5 High 10 25 0.50 1.63 0.03 1.75
鈥�
0.33 1.66 1.63
鈥�
3.37 3.34 ns
3.3 V GTL+
35 mA 35 mA High 10 25 0.50 1.57 0.03 1.80
鈥�
0.33 1.60 1.57
鈥�
3.31 3.29 ns
2.5 V GTL+
33 mA 33 mA High 10 25 0.50 1.69 0.03 1.75
鈥�
0.33 1.72 1.61
鈥�
3.43 3.32 ns
HSTL (I)
8 mA
8 mA High 20 25 0.50 2.43 0.03 2.12
鈥�
0.33 2.48 2.41
鈥�
4.19 4.12 ns
HSTL (II)
15 mA5
15 mA High 20 50 0.50 2.32 0.03 2.12
鈥�
0.33 2.36 2.08
鈥�
4.07 3.79 ns
SSTL2 (I)
15 mA 15 mA High 30 25 0.50 1.63 0.03 1.61
鈥�
0.33 1.66 1.41
鈥�
1.66 1.41 ns
SSTL2 (II)
18 mA 18 mA High 30 50 0.50 1.66 0.03 1.61
鈥�
0.33 1.69 1.36
鈥�
1.69 1.36 ns
SSTL3 (I)
14 mA 14 mA High 30 25 0.50 1.77 0.03 1.54
鈥�
0.33 1.80 1.41
鈥�
1.80 1.41 ns
SSTL3 (II)
21 mA 21 mA High 30 50 0.50 1.58 0.03 1.54
鈥�
0.33 1.61 1.28
鈥�
1.61 1.28 ns
LVDS
24 mA 24 mA High 鈥�
鈥� 0.50 1.40 0.03 1.85
鈥�
ns
LVPECL
24 mA 24 mA High 鈥�
鈥� 0.50 1.40 0.03 1.67
鈥�
ns
Notes:
1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is
卤100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the
IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for
connectivity. This resistor is not required during normal operation.
4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
5. Output drive strength is below JEDEC specification.
鐩搁棞(gu膩n)PDF璩囨枡
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