2-126 Revision 13 1.2 V DC Core Voltage Table 2-203 Register Delays Com" />
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鍨嬭櫉(h脿o)锛� A3P1000L-1FG256I
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 49/242闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 1M 256-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� ProASIC3L
RAM 浣嶇附瑷�(j矛)锛� 147456
杓稿叆/杓稿嚭鏁�(sh霉)锛� 177
闁€鏁�(sh霉)锛� 1000000
闆绘簮闆诲锛� 1.14V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 256-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 256-FPBGA锛�17x17锛�
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ProASIC3L DC and Switching Characteristics
2-126
Revision 13
1.2 V DC Core Voltage
Table 2-203 Register Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.14 V
Parameter
Description
鈥�1
Std.
Units
tCLKQ
Clock-to-Q of the Core Register
0.73
0.86
ns
tSUD
Data Setup Time for the Core Register
0.57
0.67
ns
tHD
Data Hold Time for the Core Register
0.00
ns
tSUE
Enable Setup Time for the Core Register
0.61
0.71
ns
tHE
Enable Hold Time for the Core Register
0.00
ns
tCLR2Q
Asynchronous Clear-to-Q of the Core Register
0.53
0.63
ns
tPRE2Q
Asynchronous Preset-to-Q of the Core Register
0.53
0.63
ns
tREMCLR
Asynchronous Clear Removal Time for the Core Register
0.00
ns
tRECCLR
Asynchronous Clear Recovery Time for the Core Register
0.30
0.35
ns
tREMPRE
Asynchronous Preset Removal Time for the Core Register
0.00
ns
tRECPRE
Asynchronous Preset Recovery Time for the Core Register
0.30
0.35
ns
tWCLR
Asynchronous Clear Minimum Pulse Width for the Core Register
0.30
0.34
ns
tWPRE
Asynchronous Preset Minimum Pulse Width for the Core Register
0.30
0.34
ns
tCKMPWH
Clock Minimum Pulse Width High for the Core Register
0.56
0.64
ns
tCKMPWL
Clock Minimum Pulse Width Low for the Core Register
0.56
0.64
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
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