Revision 13 2-87 Table 2-111 A3P250 Global Resource Commercial-Case Conditions: T
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鍨嬭櫉锛� A3P060-1VQG100I
寤犲晢锛� Microsemi SoC
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鏂囦欢澶�?銆�?/td> 0K
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绯诲垪锛� ProASIC3
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闁€鏁�(sh霉)锛� 60000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
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ProASIC3 Flash Family FPGAs
Revision 13
2-87
Table 2-111 A3P250 Global Resource
Commercial-Case Conditions: TJ = 70掳C, VCC = 1.425 V
Parameter
Description
鈥�2
鈥�1
Std.
Units
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2
tRCKL
Input Low Delay for Global Clock
0.80
1.01
0.91
1.15
1.07
1.36
ns
tRCKH
Input High Delay for Global Clock
0.78
1.04
0.89
1.18
1.04
1.39
ns
tRCKMPWH Minimum Pulse Width High for Global Clock
0.75
0.85
1.00
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
0.85
0.96
1.13
ns
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-112 A3P400 Global Resource
Commercial-Case Conditions: TJ = 70掳C, VCC = 1.425 V
Parameter
Description
鈥�2
鈥�1
Std.
Units
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2
tRCKL
Input Low Delay for Global Clock
0.871.090.991.241.171.46
ns
tRCKH
Input High Delay for Global Clock
0.86
1.11
0.98
1.27
1.15
1.49
ns
tRCKMPWH Minimum Pulse Width High for Global Clock
0.75
0.85
1.00
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
0.85
0.96
1.13
ns
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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