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鍨嬭櫉锛� A3P030-2QNG68I
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瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
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灏佽/澶栨锛� 68-VFQFN 瑁搁湶鐒婄洡
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ProASIC3 Flash Family FPGAs
Revision 13
2-9
Table 2-13 Summary of I/O Output Buffer Power (Per Pin) 鈥� Default I/O Software Settings 1
Applicable to Standard I/O Banks
CLOAD (pF)
VCCI (V)
Static Power
PDC3 (mW) 2
Dynamic Power
PAC10 (W/MHz) 3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
35
3.3
鈥�
431.08
3.3 V LVCMOS Wide Range4
35
3.3
鈥�
431.08
2.5 V LVCMOS
35
2.5
鈥�
247.36
1.8 V LVCMOS
35
1.8
鈥�
128.46
1.5 V LVCMOS (JESD8-11)
35
1.5
鈥�
89.46
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC3 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCC and VCCI.
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
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