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參數(shù)資料
| 型號(hào)： | A3974SED |
| 廠商： | Allegro MicroSystems, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | DMOS DUAL FULL-BRIDGE PWM MOTOR DRIVER |
| 中文描述： | 雙的DMOS全橋PWM電機(jī)驅(qū)動(dòng) |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 157K |
| 代理商： | A3974SED |
3974
DMOS DUAL FULL-BRIDGE
PWM MOTOR DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8
Current Sensing.
To minimize inaccuracies in sensing the
I
current level caused by ground-trace IR drops, the sense
resistor should have an independent ground return to a ground
terminal of the device. For low-value sense resistors, the IR
drops in the PCB sense traces of the resistor can be significant
and should be taken into account. The use of sockets should be
avoided as they can introduce variation in R
S
due to their
contact resistance.
The maximum value of R
S
is given as R
S
= 0.5/I
TRIPMAX
.
Braking.
The braking function is implemented by driving the
device in slow-decay mode via serial port bit D13, enabling
synchronous rectification via bits D11 and D12, and applying
an enable chop command with the combination of D14 and the
ENABLE input terminal. Because it is possible to drive current
in both directions through the DMOS switches, this configura-
tion effectively shorts out the motor-generated BEMF as long as
the ENABLE chop mode is asserted. It is important to note that
the internal PWM current-control circuit will not limit the
current when braking, because the current does not flow
through the sense resistor. The maximum brake current can be
approximated by V
/R
. Care should be taken to ensure that
the maximum ratings of the device are not exceeded in worst-
case braking situations of high speed and high inertial loads.
A.
Minimum Data Setup Time...........................................15 ns
B.
Minimum Data Hold Time ............................................10 ns
C.
Minimum Setup Strobe to Clock Rising Edge .......... 50 ns
D.
Minimum Clock High Pulse Width ........................... 50 ns
E.
Minimum Clock Low Pulse Width............................ 50 ns
F.
Minimum Setup Clock Rising Edge to Strobe........... 50 ns
G.
Minimum Strobe Pulse Width................................... 50 ns
DATA
CLOCK
Dwg. WP-038
STROBE
A
F
B
G
C
D
E
D19
D0
D18
APPLICATIONS INFORMATION
Thermal protection
.
Circuitry turns off all drivers when the
junction temperature reaches 165
°
C typically. It is intended
only to protect the device from failures due to excessive
junction temperatures and should not imply that output short
circuits are permitted. Thermal shutdown has a hysteresis of
approximately 15
°
C.
Layout.
The printed wiring board should use a heavy ground
plane. For optimum electrical and thermal performance, the
driver should be soldered directly onto the board. The ground
side of R
should have an individual path to a ground terminal
of the device. This path should be as short as is possible
physically and should not have any other components con-
nected to it. The load supply terminal, V
, should be
decoupled with an electrolytic capacitor (>47
μ
F is recom-
mended) placed as close to the device as is possible.
Serial Port Write Timing Operation.
Data is clocked into
shift register on the rising edge of CLOCK signal. Normally,
STROBE will be held high, and only will be brought low to
initiate a write cycle. Refer to diagram below and specification
table for timing requirements.
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