參數(shù)資料
型號: A3936SED
廠商: Allegro MicroSystems, Inc.
元件分類: 基準電壓源/電流源
英文描述: DMOS THREE-PHASE PWM MOTOR DRIVER
中文描述: 的DMOS三相PWM電機驅(qū)動
文件頁數(shù): 6/9頁
文件大?。?/td> 177K
代理商: A3936SED
3936 Three Phase PWM Motor Driver
Functional Description
VREG.
The VREG pin should be decoupled with a 0.22
μ
F capacitor to ground. This supply voltage is used to run
the sink side DMOS outputs. VREG is internally monitored
and in the case of a fault condition, the outputs of the device
are disabled.
Charge Pump.
The Charge Pump is used to generate a
supply above VBBto drive the source side DMOS gates. A
0.22 uF ceramic monolithic capacitor should be connected
between CP
1
and CP
2
for pumping purposes. A 0.22 uF
ceramic monolithic capacitor should be connected between
V
CP
and VBB to act as a reservoir to run the high side
DMOS devices. The V
CP
Voltage is internally monitored
and in the case of a fault condition the outputs of the device
are disabled.
Shutdown.
In the event of a fault due to excessive
junction temperature, or low voltage on V
CP
or V
REG
, the
outputs of the device are disabled until the fault condition is
removed. At power up, and in the event of low V
DD
, the
UVLO circuit disables the drivers.
Current Regulation.
Load current is regulated by an
internal fixed off time PWM control circuit. When the
outputs of the DMOS H-bridge are turned on, current
increases in the motor winding until it reaches a value given
by:
I
TRIP
= V
REF
/(10*R
SENSE
)
At the trip point, the sense comparator resets the source
enable latch, turning off the source driver. At this point,
load inductance causes the current to recirculate for the
fixed off time period. The current path during recirculation
is determined by the configuration of slow/mixed decay
mode and the synchronous rectification control setting.
Enable Logic.
The Enable input terminal allows
external PWM. ENABLE high turns ON the selected sink-
source pair, enable low switches off the appropriate drivers
and the load current decays. If the ENABLE pin is held
high, the current will rise until it reaches the level set by the
internal current control circuit.
ENABLE
0
Outputs
Source
Chopped
ON
1
Extmode Logic.
When using external PWM current
control, the EXTMODE input determines the current path
during the chopped cycle. With EXTMODE set low, fast
decay mode, both the source and sink drivers are chopped
OFF during the decay time (ENABLE=0). With
EXTMODE high, slow decay mode, only the source driver
turns off during the current decay time.
EXTMODE
0
1
Decay
Fast
Slow
Sleep Mode.
The input pin SLEEP is dedicated to put
the device into a minimum current draw mode. When
asserted low, all circuits are disabled.
Fixed Off-Time.
The 3936 is set for a fixed off time of
96 counts of the internal oscillator, typically 24
μ
s with
4Mhz oscillator.
Internal Current Control Mode.
Input pins PFD1
and PFD2 determine the current decay method after an
overcurrent event is detected at sense input. In slow decay
mode both sink side drivers are turned on for the fixed off
time period. Mixed decay mode starts out in fast decay
mode for the selected percentage of the fixed off time, and
then is followed by slow decay for the rest of the period.
PFD2
0
0
1
1
PFD1
0
1
0
1
% t
OFF
0
15
48
100
Decay
Slow
Mixed
Mixed
Fast
相關PDF資料
PDF描述
A3936SED-T DMOS THREE-PHASE PWM MOTOR DRIVER
A3938 Three-Phase Power MOSFET Controller
A3938SEQ Three-Phase Power MOSFET Controller
A3938SLD Three-Phase Power MOSFET Controller
A3938SLD-T Three-Phase Power MOSFET Controller
相關代理商/技術參數(shù)
參數(shù)描述
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