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| 型號： | A3282LLHLT-T |
| 廠商： | Allegro Microsystems Inc |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 491K |
| 描述： | IC SW HALL EFFECT CHOPPER SOT23W |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 傳感范圍： | 150G 跳閘，-150G 釋放 |
| 類型： | 雙極卡鎖 |
| 電源電壓： | 3.6 V ~ 24 V |
| 電流 - 電源： | 3.5mA |
| 電流 - 輸出（最大）： | 25mA |
| 輸出類型： | 數(shù)字，開路集電極 |
| 特點(diǎn)： | 穩(wěn)壓電壓 |
| 工作溫度： | -40°C ~ 150°C |
| 封裝/外殼： | SOT-23W |
| 供應(yīng)商設(shè)備封裝： | SOT-23W |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 620-1055-6 |
Chopper-Stabilized Hall Effect Latch
A3282
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The device must be operated below the maximum junction
temperature of the device, T
J(max)
. Under certain combinations of
peak conditions, reliable operation may require derating sup-
plied power or improving the heat dissipation properties of the
application. This section presents a procedure for correlating
factors affecting operating T
J
. (Thermal data is also available on
the Allegro MicroSystems Web site.)
The Package Thermal Resistance, R
qJA
, is a gure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity,
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, R
qJC
, is
relatively small component of R
qJA
. Ambient air temperature,
T
A
, and air motion are signi cant external factors, damped by
overmolding.
The effect of varying power levels (Power Dissipation, P
D
), can
be estimated. The following formulas represent the fundamental
relationships used to estimate T
J
, at P
D
.
P
D
= V
IN
?/DIV>
I
IN
(1)
DT = P
D
?/DIV>
R
qJA
(2)
T
J
= T
A
+ 擳 (3)
For example, given common conditions such as: T
A
= 25癈,
V
CC
= 12 V, I
CC
= 1.5 mA, and R
qJA
= 165 癈/W, then:
P
D
= V
CC
?/DIV>
I
CC
= 12 V
?/DIV>
1.5 mA = 18 mW
DT = P
D
?/DIV>
R
qJA
= 18 mW
?/DIV>
165 癈/W = 3癈
T
J
= T
A
+ DT = 25癈 + 3癈 = 28癈
A worst-case estimate, P
D(max)
, represents the maximum allow-
able power level (V
CC(max)
, I
CC(max)
), without exceeding T
J(max)
,
at a selected R
qJA
and T
A
.
Example: Reliability for V
CC
at T
A
=
150癈, package LH, using a
low-K PCB.
Observe the worst-case ratings for the device, speci cally:
R
qJA
=
228 癈/W, T
J(max)
=
165癈, V
CC(max)
=
24 V, and
I
CC(max)
=
5
mA.
Calculate the maximum allowable power level, P
D(max)
. First,
invert equation 3:
DT
max
= T
J(max)
T
A
= 165
癈
150
癈 = 15
癈
This provides the allowable increase to T
J
resulting from internal
power dissipation. Then, invert equation 2:
P
D(max)
= DT
max
?R
qJA
= 15癈 ?228 癈/W = 66 mW
Finally, invert equation 1 with respect to voltage:
V
CC(est)
= P
D(max)
? I
CC(max)
= 66 mW ?5 mA = 13 V
The result indicates that, at T
A
, the application and device can
dissipate adequate amounts of heat at voltages dV
CC(est)
.
Compare V
CC(est)
to V
CC(max)
. If V
CC(est)
d V
CC(max)
, then reli-
able operation between V
CC(est)
and V
CC(max)
requires enhanced
R
qJA
. If V
CC(est)
e V
CC(max)
, then operation between V
CC(est)
and
V
CC(max)
is reliable under these conditions.
Power Derating
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