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參數(shù)資料
| 型號： | A29L800AUG-70U |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 1M X 8 Bit / 512K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory |
| 中文描述： | 100萬× 8位/ 16位為512k ×電壓的CMOS 3.0只，引導扇區(qū)閃存 |
| 文件頁數(shù)： | 12/36頁 |
| 文件大小： | 503K |
| 代理商： | A29L800AUG-70U |
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A29L800A Series
(June, 2005, Version 1.1)
11
AMIC Technology, Corp.
START
Write Program
Command
Sequence
Data Poll
from System
Verify Data
Last Address
Programming
Completed
No
Yes
Yes
Increment Address
Embedded
Program
algorithm in
progress
Note : See the appropriate Command Definitions table for
program command sequence.
Figure 1. Program Operation
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes
or words to the device faster than using the standard program
command sequence. The unlock bypass command sequence
is initiated by first writing two unlock cycles. This is followed by
a third write cycle containing the unlock bypass command, 20h.
The device then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program command, A0h;
the second cycle contains the program address and data.
Additional data is programmed in the same manner. This mode
dispenses with the initial two unlock cycles required in the
standard program command sequence, resulting in faster total
programming time. Table 5 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid. To
exit the unlock bypass mode, the system must issue the two-
cycle unlock bypass reset command sequence. The first cycle
must contain the data 90h; the second cycle the data 00h.
Addresses are don’t care for both cycle. The device returns to
reading array data.
Figure 1 illustrates the algorithm for the program operation. See
the Erase/Program Operations in “AC Characteristics” for
parameters, and to Program Operation Timings for timing
diagrams.
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which in
turn invokes the Embedded Erase algorithm. The device does
not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any
controls or timings during these operations. The Command
Definitions table shows the address and data requirements for
the chip erase command sequence.
Any commands written to the chip during the Embedded Erase
algorithm are ignored. The system can determine the status of
the erase operation by using I/O
7
, I/O
6
, or I/O
2
. See "Write
Operation Status" for information on these status bits. When the
Embedded Erase algorithm is complete, the device returns to
reading array data and addresses are no longer latched.
Figure 2 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in "AC Characteristics" for
parameters, and to the Chip/Sector Erase Operation Timings
for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements for
the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not required
to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out
of 50
μ
s begins. During the time-out period, additional sector
addresses and sector erase commands may be written.
Loading the sector erase buffer may be done in any sequence,
and the number of sectors may be from one sector to all
sectors. The time between these additional cycles must be less
than 50
μ
s, otherwise the last address and command might not
be accepted, and erasure may begin. It is recommended that
processor interrupts be disabled during this time to ensure all
commands are accepted. The interrupts can be re-enabled after
the last Sector Erase command is written. If the time between
additional sector erase commands can be assumed to be less
than 50
μ
s, the system need not monitor I/O
3
. Any command
other than Sector Erase or Erase Suspend during the time-out
period resets the device to reading array data. The system must
rewrite the command sequence and any additional sector
addresses and commands.
The system can monitor I/O
3
to determine if the sector erase
timer has timed out. (See the " I/O
3
: Sector Erase Timer"
相關PDF資料 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A29L800AUG-70UF | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 8 Bit / 512K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory |
| A29L800AUG-90 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 8 Bit / 512K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory |
| A29L800AUG-90F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 8 Bit / 512K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory |
| A29L800AUG-90U | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 8 Bit / 512K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory |
| A29L800AUG-90UF | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 8 Bit / 512K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory |
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