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參數(shù)資料
| 型號： | A29L320 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 4M X 8 Bit / 2M X 16 Bit CMOS 3.3 Volt-only, Boot Sector Flash Memory |
| 中文描述： | 4米× 8位/ 2米× 16位CMOS 3.3伏只，引導(dǎo)扇區(qū)閃存 |
| 文件頁數(shù)： | 22/44頁 |
| 文件大小： | 588K |
| 代理商： | A29L320 |
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A29L320 Series
PRELIMINARY
(September, 2005, Version 0.0)
21
AMIC Technology, Corp.
Write Operation Status
Several bits, I/O
2
, I/O
3
, I/O
5
, I/O
6
, I/O
7,
RY/
BY
are provided in
the A29L320 to determine the status of a write operation.
Table 10 and the following subsections describe the
functions of these status bits. I/O
7
, I/O
6
and RY/
BY
each
offer a method for determining whether a program or erase
operation is complete or in progress. These three bits are
discussed first.
I/O
7
:
Data
Polling
The
Data
Polling bit, I/O
7
, indicates to the host system
whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend.
Data
Polling is
valid after the rising edge of the final
WE
pulse in the
program or erase command sequence.
During the Embedded Program algorithm, the device outputs
on I/O
7
the complement of the datum programmed to I/O
7
.
This I/O
7
status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O
7
.
The system must provide the program address to read valid
status information on I/O
7
. If a program address falls within a
protected sector,
Data
Polling on I/O
7
is active for
approximately 2
μ
s, then the device returns to reading array
data.
During the Embedded Erase algorithm,
Data
Polling
produces a "0" on I/O
7
. When the Embedded Erase algorithm
is complete, or if the device enters the Erase Suspend mode,
Data
Polling produces a "1" on I/O
7
.This is analogous to the
complement/true datum output described for the Embedded
Program algorithm: the erase function changes all the bits in
a sector to "1"; prior to this, the device outputs the
"complement," or "0." The system must provide an address
within any of the sectors selected for erasure to read valid
status information on I/O
7
.
After an erase command sequence is written, if all sectors
selected for erasing are protected,
Data
Polling on I/O
7
is
active for approximately 100
μ
s, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
When the system detects I/O
7
has changed from the
complement to true data, it can read valid data at I/O
7
- I/O
0
on the following read cycles. This is because I/O
7
may
change asynchronously with I/O
0
- I/O
6
while Output Enable
(
OE
) is asserted low. The
Data
Polling Timings (During
Embedded Algorithms) figure in the "AC Characteristics"
section illustrates this. Table 10 shows the outputs for
Data
Polling on I/O
7
. Figure 5 shows the
Data
Polling algorithm.
START
Read I/O
7
-I/O
0
Address = VA
I/O
7
= Data
FAIL
No
Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. I/O
7
should be rechecked even if I/O
5
= "1" because
I/O
7
may change simultaneously with I/O
5
.
No
Read I/O
7
- I/O
0
Address = VA
I/O
5
= 1
I/O
7
= Data
Yes
No
PASS
Yes
Yes
Figure 5. Data Polling Algorithm
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