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參數(shù)資料
| 型號： | A29L040-70 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 512K X 8 Bit CMOS 3.0 Volt-only, Uniform Sector Flash Memory |
| 中文描述： | 為512k × 8位CMOS 3.0伏只，統(tǒng)一部門快閃記憶體 |
| 文件頁數(shù)： | 9/32頁 |
| 文件大?。?/td> | 303K |
| 代理商： | A29L040-70 |
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A29L040 Series
PRELIMINARY (June, 2003, Version 0.1)
8
AMIC Technology, Corp.
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase.
The Embedded Erase algorithm automatically preprograms
and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to
provide any controls or timings during these operations. The
Command Definitions table shows the address and data
requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. The system can determine the
status of the erase operation by using I/O
7
, I/O
6
, or I/O
2
. See
"Write Operation Status" for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no
longer latched.
Figure 2 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in "AC Characteristics"
for parameters, and to the Chip/Sector Erase Operation
Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements
for the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-
out of 50
μ
s begins. During the time-out period, additional
sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one
sector to all sectors. The time between these additional
cycles must be less than 50
μ
s, otherwise the last address
and command might not be accepted, and erasure may
begin. It is recommended that processor interrupts be
disabled during this time to ensure all commands are
accepted. The interrupts can be re-enabled after the last
Sector Erase command is written. If the time between
additional sector erase commands can be assumed to be
less than 50
μ
s, the system need not monitor I/O
3
. Any
command other than Sector Erase or Erase Suspend during
the time-out period resets the device to reading array data.
The system must rewrite the command sequence and any
additional sector addresses and commands.
The system can monitor I/O
3
to determine if the sector erase
timer has timed out. (See the " I/O
3
: Sector Erase Timer"
section.) The time-out begins from the rising edge of the final
WE
pulse in the command sequence.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are
ignored.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no
longer latched. The system can determine the status of the
erase operation by using I/O
7
, I/O
6
, or I/O
2
. Refer to "Write
Operation Status" for information on these status bits.
START
Write Program
Command
Sequence
Data Poll
from System
Verify Data
Last Address
Programming
Completed
No
Yes
Yes
Increment Address
Embedded
Program
algorithm in
progress
Note : See the appropriate Command Definitions table for
program command sequence.
Figure 1. Program Operation
相關PDF資料 |
PDF描述 |
|---|---|
| A29L040L-70 | 512K X 8 Bit CMOS 3.0 Volt-only, Uniform Sector Flash Memory |
| A29L040V-70 | 512K X 8 Bit CMOS 3.0 Volt-only, Uniform Sector Flash Memory |
| A29L040X-70 | 512K X 8 Bit CMOS 3.0 Volt-only, Uniform Sector Flash Memory |
| A29L040AY-70 | FUSE,SIBA,70 125 40,.5A/700V RoHS Compliant: NA |
| A29L040AY-70F | ROTARY-SCALE AC CLAMP-ON MULTIMETERS ACCESSORIES FOR RS SERIES CLAMP-ON METERS RoHS Compliant: NA |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A29L040-70F | 制造商:AMIC Technology 功能描述:MEMORY FLASH NOR 3V 4M 32DIP |
| A29L040A | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 8 Bit CMOS 3.0 Volt-only, Uniform Sector Flash Memory |
| A29L040A-70 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 8 Bit CMOS 3.0 Volt-only, Uniform Sector Flash Memory |
| A29L040A-70F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 8 Bit CMOS 3.0 Volt-only, Uniform Sector Flash Memory |
| A29L040AL | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 8 Bit CMOS 3.0 Volt-only, Uniform Sector Flash Memory |
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