參數(shù)資料
型號: A29DL324UG-80
廠商: AMIC Technology Corporation
英文描述: 32 Megabit (4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
中文描述: 32兆位(4米× 8-Bit/2M x 16位),3.0伏的CMOS只,同時作業(yè)快閃記憶體
文件頁數(shù): 5/46頁
文件大?。?/td> 556K
代理商: A29DL324UG-80
A29DL324 Series
PRELIMINARY (May, 2002, Version 0.0)
5
AMIC Technology, Inc.
Absolute Maximum Ratings*
Storage Temperature (T
stg
) . . . . . . . . . . -55
°
C to + 125
°
C
Operating Ambient Temperature (T
A
) . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
°
C to + 85
°
C
Input / Output Voltage with Respect to GND
WP
(ACC),
RESET
. . . . . . . . . . . . -0.5V
Note1
to 13.0V
All Pins except
WP
(ACC),
RESET
. . . . . . . . . . . . . . .
. . . . . . . . . . . . . -0.5V
Note1
to VCC + 0.4 (4.0V max.)
Note2
Supply Voltage with Respect to GND (VCC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.0V
Notes:
1. -2.0V (Min.) (Pulse width
20ns)
2. VCC + 0.5V (Max.) (Pulse width
20ns)
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
Recommended Operating Conditions
Operating Ambient Temperature (T
A
) . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
°
C to +85
°
C
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . +2.7V to +3.6V
Bus Operations
The following table shows the operation modes of the dual
operation flash memory. Before turning on power, input
GND
±
0.2 V to the
RESET
until VCC
VCC (min.).
Table 1. A29DL324 Bus Operations
Operation
CE
OE
WE
I/O
15
,
A-1
A-1
X
A-1
X
X
X
X
X
A6
A1
A0
I/O
0
to
I/O
7
Data output
Data output
Data input
Data input
Hi-Z
Hi-Z
Hi-Z
Hi-Z or
Data input / output
Data output
Data output
Hi-Z or
Data input / output
Data input
Data input
I/O
8
to
I/O
15
RESET
WP
(ACC)
X
X
Note3
Note3
X
X
X
Note3
BYTE mode
WORD mode
BYTE mode
WORD mode
L
L
L
L
H
X
L
X
L
L
H
H
X
X
H
X
H
H
L
L
X
X
H
X
Address input
Address input
Address input
Address input
X
X
X
X
X
X
X
X
Hi-Z
H
H
H
H
H
L
H
V
ID
Read (Note)
Write
Standby
Hardware reset / Standby
Output Disable
Temporary Sector Group Unprotect
Hi-Z
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
BYTE mode
WORD mode
L
L
X
L
L
X
H
H
X
A-1
X
X
Address input
Address input
X
X
Hi-Z
H
H
X
X
X
L
Automatic Sleep
Mode
Boot Block Sector Protect
X
BYTE mode
WORD mode
L
L
H
H
L
L
A-1
X
Address input
Address input
Hi-Z
H
H
VACC
VACC
Accelerated Mode
Note: When
OE
= V
IL
, V
IL
can be applied to
WE
. When
OE
= V
IH
, a write operation is started.
Remarks: 1. H : V
IH
, L : V
IL
, : V
IH
or V
IL
, V
ID
: 11.5 V to 12.5 V, VACC : 8.5 V to 9.5 V
2. If an address is held longer than the minimum read cycle time (t
RC
), the automatic sleep mode is set.
3. If
WP
(ACC)=V
IL
, sector 0,1,140, and 141 remain protected. If
WP
(ACC)=V
IH
,
protection on sectors 0,1,140, and 141
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If
WP
(ACC)=V
HH
, all sectors will be unprotected.
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