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參數(shù)資料
| 型號(hào)： | A29512V-90 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 64K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| 中文描述： | 64K的× 8位CMOS 5.0伏只，統(tǒng)一部門快閃記憶體 |
| 文件頁數(shù)： | 2/31頁 |
| 文件大?。?/td> | 293K |
| 代理商： | A29512V-90 |
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A29512 Series
64K X 8 Bit CMOS 5.0 Volt-only,
Uniform Sector Flash Memory
Preliminary
Features
n
5.0V
±
10% for read and write operations
n
Access times:
- 55/70/90 (max.)
n
Current:
- 20 mA typical active read current
- 30 mA typical program/erase current
- 1
μ
A typical CMOS standby
n
Flexible sector architecture
-
32 Kbyte X 2 sectors
-
Any combination of sectors can be erased
-
Supports full chip erase
-
Sector protection:
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within
that sector
n
Embedded Erase Algorithms
- Embedded Erase algorithm will automatically erase
the entire chip or any combination of designated
sectors and verify the erased sectors
General Description
PRELIMINARY (November, 2001, Version 0.0)
1
AMIC Technology, Inc.
- Embedded Program algorithm automatically writes
and verifies bytes at specified addresses
n
Typical 100,000 program/erase cycles per sector
n
20-year data retention at 125
°
C
- Reliable operation for the life of the system
n
Compatible with JEDEC-standards
- Pinout and software compatible with single-power-
supply Flash memory standard
-
Superior inadvertent write protection
n
Data
Polling and toggle bits
-
Provides a software method of detecting completion
of program or erase operations
n
Erase Suspend/Erase Resume
-
Suspends a sector erase operation to read data
from, or program data to, a non-erasing sector, then
resumes the erase operation
n
Package options
-
32-pin P-DIP, PLCC, or TSOP(Forward type)
The A29512 is a 5.0 volt-only Flash memory organized as
65,535 bytes of 8 bits each. The 64 Kbytes of data are further
divided into four sectors for flexible sector erase capability.
The 8 bits of data appear on I/O
0
- I/O
7
while the addresses
are input on A0 to A15. The A29512 is offered in 32-pin
PLCC, TSOP, and PDIP packages. This device is designed
to be programmed in-system with the standard system 5.0
volt VCC supply. Additional 12.0 volt VPP is not required for
in-system write or erase operations. However, the A29512
can also be programmed in standard EPROM programmers.
The A29512 has the first toggle bit, I/O
6
, which indicates
whether an Embedded Program or Erase is in progress, or it
is in the Erase Suspend. Besides the I/O
6
toggle bit, the
A29512 has a second toggle bit, I/O
2
, to indicate whether the
addressed sector is being selected for erase. The A29512
also offers the ability to program in the Erase Suspend mode.
The standard A29512 offers access times of 55, 70 and 90
ns allowing high-speed microprocessors to operate without
wait states. To eliminate bus contention the device has
separate chip enable (
CE
), write enable (
WE
) and output
enable (
OE
) controls.
The device requires only a single 5.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
The A29512 is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin.
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