參數(shù)資料
型號(hào)： A29040V-150
廠商： AMIC Technology Corporation
英文描述： 512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory
中文描述： 為512k × 8位CMOS 5.0伏只，統(tǒng)一部門快閃記憶體
文件頁數(shù)： 4/30頁
文件大?。?/td> 285K
代理商： A29040V-150
A29040A Series
PRELIMINARY (August, 2001, Version 0.1)
4
AMIC Technology, Inc.
Absolute Maximum Ratings*
Ambient Operating Temperature . . . . . -55
°
C to + 125
°
C
Storage Temperature . . . . . . . . . . . . . . -65
°
C to + 125
°
C
VCC to Ground . . . . . . . . . . . . . . . . . . . . . . -2.0V to 7.0V
Output Voltage (Note 1) . . . . . . . . . . . . . . . -2.0V to 7.0V
A9 &
OE
(Note 2) . . . . . . . . . . . . . . . . . . . -2.0V to 12.5V
All other pins (Note 1) . . . . . . . . . . . . . . . . . -2.0V to 7.0V
Output Short Circuit Current (Note 3) . . . . . . . . . . 200mA
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5V.
During voltage transitions, inputs may undershoot VSS
to -2.0V for periods of up to 20ns. Maximum DC voltage
on output and I/O pins is VCC +0.5V. During voltage
transitions, outputs may overshoot to VCC +2.0V for
periods up to 20ns.
2. Minimum DC input voltage on A9 pins is -0.5V. During
voltage transitions, A9 and
OE
may overshoot VSS to
-2.0V for periods of up to 20ns. Maximum DC input
voltage on A9 and
OE
is +12.5V which may overshoot
to 13.5V for periods up to 20ns.
3. No more than one output is shorted at a time. Duration
of the short circuit should not be greater than one
second.
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
Operating Ranges
Commercial (C) Devices
Ambient Temperature (T
A
) . . . . . . . . . . . . . 0
°
C to +70
°
C
VCC Supply Voltages
VCC for
±
10% devices . . . . . . . . . . . . . +4.5V to +5.5V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
Device Bus Operations
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location. The
register is composed of latches that store the commands,
along with the address and data information needed to
execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine
outputs dictate the function of the device. The appropriate
device bus operations table lists the inputs and control
levels required, and the resulting output. The following
subsections describe each of these operations in further
detail.
Table 1. A29040A Device Bus Operations
Operation
CE
OE
WE
A0 – A18
I/O
0
- I/O
7
Read
L
L
H
A
IN
D
OUT
Write
L
H
L
A
IN
D
IN
CMOS Standby
VCC
±
0.5 V
X
X
X
High-Z
TTL Standby
H
X
X
X
High-Z
Output Disable
L
H
H
X
High-Z
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
±
0.5V, X = Don't Care, D
IN
= Data In, D
OUT
= Data Out, A
IN
= Address In
Note: See the "Sector Protection/Unprotection" section, for more information.
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