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參數(shù)資料
| 型號(hào)： | A29040BL-55U |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| 中文描述： | 為512k × 8位CMOS 5.0伏只，統(tǒng)一部門快閃記憶體 |
| 文件頁數(shù)： | 9/29頁 |
| 文件大小： | 392K |
| 代理商： | A29040BL-55U |
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A29040B Series
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase.
The Embedded Erase algorithm automatically preprograms
and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to
provide any controls or timings during these operations. The
Command Definitions table shows the address and data
requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. The system can determine the
status of the erase operation by using I/O
7
, I/O
6
, or I/O
2
. See
"Write Operation Status" for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no
longer latched.
Figure 2 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in "AC Characteristics"
for parameters, and to the Chip/Sector Erase Operation
Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements
for the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-
out of 50
μ
s begins. During the time-out period, additional
sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one
sector to all sectors. The time between these additional
cycles must be less than 50
μ
s, otherwise the last address
and command might not be accepted, and erasure may
begin. It is recommended that processor interrupts be
disabled during this time to ensure all commands are
accepted. The interrupts can be re-enabled after the last
Sector Erase command is written. If the time between
additional sector erase commands can be assumed to be
less than 50
μ
s, the system need not monitor I/O
3
. Any
command other than Sector Erase or Erase Suspend during
the time-out period resets the device to reading array data.
The system must rewrite the command sequence and any
additional sector addresses and commands.
The system can monitor I/O
3
to determine if the sector erase
timer has timed out. (See the " I/O
3
: Sector Erase Timer"
section.) The time-out begins from the rising edge of the final
WE
pulse in the command sequence.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are
ignored.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no
longer latched. The system can determine the status of the
erase operation by using I/O
7
, I/O
6
, or I/O
2
. Refer to "Write
Operation Status" for information on these status bits.
Figure 2 illustrates the algorithm for the erase operation.
Refer to the Erase/Program Operations tables in the "AC
Characteristics" section for parameters, and to the Sector
Erase Operations Timing diagram for timing waveforms.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt
a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. This
command is valid only during the sector erase operation,
including the 50
μ
s time-out period during the sector erase
command sequence. The Erase Suspend command is
ignored if written during the chip erase operation or
Embedded Program algorithm. Writing the Erase Suspend
command during the Sector Erase time-out immediately
terminates the time-out period and suspends the erase
operation. Addresses are "don't cares" when writing the
Erase Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum of
20
μ
s to suspend the erase operation. However, when the
Erase Suspend command is written during the sector erase
time-out, the device immediately terminates the time-out
period and suspends the erase operation.
After the erase operation has been suspended, the system
can read array data from or program data to any sector not
selected for erasure. (The device "erase suspends" all
sectors selected for erasure.) Normal read and write timings
and command definitions apply. Reading at any address
within erase-suspended sectors produces status data on
I/O
7
- I/O
0
. The system can use I/O
7
, or I/O
6
and I/O
2
together, to determine if a sector is actively erasing or is
erase-suspended. See "Write Operation Status" for
information on these status bits.
After an erase-suspended program operation is complete,
the system can once again read array data within non-
suspended sectors. The system can determine the status of
the program operation using the I/O
7
or I/O
6
status bits, just
as in the standard program operation. See "Write Operation
Status" for more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend mode.
The device allows reading autoselect codes even at
addresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
"Autoselect Command Sequence" for more information.
The system must write the Erase Resume command
(address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another Erase
Suspend command can be written after the device has
resumed erasing.
PRELIMINARY
(December, 2004, Version 0.2)
8
AMIC Technology, Corp.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A29040B | 512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| A29040B-55 | 512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| A29040B-55F | 512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| A29040B-55U | 512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| A29040B-70 | 512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A29040BL-55UF | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| A29040BL-70 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| A29040BL-70F | 制造商:AMIC Technology 功能描述:IC SM FLASH 4MB 5V 制造商:AMIC Technology 功能描述:IC, SM, FLASH, 4MB, 5V 制造商:AMIC Technology 功能描述:MEMORY, FLASH, 4MBIT, 70NS, PLCC-32; Memory Type:Flash; Memory Size:4Mbit; Memory Configuration:512K x 8; Supply Voltage Min:4.5V; Supply Voltage Max:5.5V; Memory Case Style:PLCC; No. of Pins:32; Access Time:70ns; IC Interface Type:-;RoHS Compliant: Yes 制造商:AMIC Technology 功能描述:NOR Flash Parallel 5V 4Mbit 512K x 8bit 70ns 32-Pin PLCC |
| A29040BL-70U | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| A29040BL-70UF | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
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