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參數(shù)資料
| 型號(hào)： | A29040AL-90 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| 中文描述： | 為512k × 8位CMOS 5.0伏只，統(tǒng)一部門快閃記憶體 |
| 文件頁數(shù)： | 12/30頁 |
| 文件大?。?/td> | 285K |
| 代理商： | A29040AL-90 |
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A29040A Series
PRELIMINARY (August, 2001, Version 0.1)
12
AMIC Technology, Inc.
I/O
6
: Toggle Bit I
Toggle Bit I on I/O
6
indicates whether an Embedded Program
or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I may
be read at any address, and is valid after the rising edge of the
final
WE
pulse in the command sequence (prior to the
program or erase operation), and during the sector erase time-
out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O
6
to toggle.
(The system may use either
OE
or
CE
to control the read
cycles.) When the operation is complete, I/O
6
stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O
6
toggles for
approximately 100
μ
s, then returns to reading array data. If not
all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O
6
and I/O
2
together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O
6
toggles. When the device
enters the Erase Suspend mode, I/O
6
stops toggling. However,
the system must also use I/O
2
to determine which sectors are
erasing or erase-suspended. Alternatively, the system can use
I/O
7
(see the subsection on " I/O
7
:
Data
Polling").
If a program address falls within a protected sector, I/O
6
toggles for approximately 2
μ
s after the program command
sequence is written, then returns to reading array data.
I/O
6
also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for Toggle
Bit I on I/O
6
. Refer to Figure 4 for the toggle bit algorithm, and
to the Toggle Bit Timings figure in the "AC Characteristics"
section for the timing diagram. The I/O
2
vs. I/O
6
figure shows
the differences between I/O
2
and I/O
6
in graphical form. See
also the subsection on " I/O
2
: Toggle Bit II".
I/O
2
: Toggle Bit II
The "Toggle Bit II" on I/O
2
, when used with I/O
6
, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final
WE
pulse in the command sequence.
I/O
2
toggles when the system reads at addresses within those
sectors that have been selected for erasure. (The system may
use either
OE
or
CE
to control the read cycles.) But I/O
2
cannot distinguish whether the sector is actively erasing or is
erase-suspended. I/O
6
, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information. Refer
to Table 5 to compare outputs for I/O
2
and I/O
6
.
Figure 4 shows the toggle bit algorithm in flowchart form, and
the section " I/O
2
: Toggle Bit II" explains the algorithm. See
also the " I/O
6
: Toggle Bit I" subsection. Refer to the Toggle Bit
Timings figure for the toggle bit timing diagram. The I/O
2
vs.
I/O
6
figure shows the differences between I/O
2
and I/O
6
in
graphical form.
Reading Toggle Bits I/O
6
, I/O
2
Refer to Figure 4 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O
7
- I/O
0
at least twice in a row to determine whether a toggle
bit is toggling. Typically, a system would note and store the
value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can
read array data on I/O
7
- I/O
0
on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O
5
is high (see the section
on I/O
5
). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have
stopped toggling just as I/O
5
went high. If the toggle bit is no
longer toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the device did
not complete the operation successfully, and the system must
write the reset command to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O
5
has not gone high. The
system may continue to monitor the toggle bit and I/O
5
through
successive read cycles, determining the status as described in
the previous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine the
status of the operation (top of Figure 4).
I/O
5
: Exceeded Timing Limits
I/O
5
indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions I/O
5
produces a "1." This is a failure condition that
indicates the program or erase cycle was not successfully
completed.
The I/O
5
failure condition may appear if the system tries to
program a "1 "to a location that is previously programmed to
"0." Only an erase operation can change a "0" back to a "1."
Under this condition, the device halts the operation, and when
the operation has exceeded the timing limits, I/O
5
produces a
"1."
Under both these conditions, the system must issue the reset
command to return the device to reading array data.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A29040-70 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Crimp; Body Material:Aluminum; Series:PT07; No. of Contacts:10; Connector Shell Size:12; Connecting Termination:Crimp; Circular Shell Style:Jam Nut Receptacle; Body Style:Straight |
| A29040-90 | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVS06; Number of Contacts:22; Connector Shell Size:13; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight |
| A29040AV-70 | Test RoHS Compliant: NA |
| A29040AV-90 | AUTOMATIC 600A CLAMPMETER WITH AUTOTECT RoHS Compliant: NA |
| A29040V-120 | Linear Array Light; LED Color:Red; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:627nm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A29040ASERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512K X 8 Bit CMOS 5.0 Volt-only. Uniform Sector Flash Memory |
| A29040AV-55 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| A29040AV-70 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| A29040AV-90 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| A29040B | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
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