
Accelerator Series FPGAs – ACT 3 Family
R e visio n 3
2 - 17
Figure 2-11 Output Buffers
Figure 2-12 AC Test Loads
Figure 2-13 Input Buffer Delays
To AC test loads (shown below)
PAD
D
E
TRIBUFF
In
VCC
GND
50%
Out
VOL
VOH
1.5 V
tDHS,
50%
1.5 V
tDHS
En
VCC
GND
50%
Out
VOL
1.5 V
tENZHS,
50%
10%
tENHSZ
En
VCC
GND
50%
Out
GND
VOH
1.5 V
tENZHS,
50%
90%
tENHSZ
VCC
Load 1
(Used to measure propagation delay)
Load 2
(Used to measure rising/falling edges)
35 pF
To the output under test
VCC
GND
35 pF
To the output under test
R to VCCfor t
PLZ / tPZL
R to GND for t
PHZ / tPZH
R = 1 k
Ω
PAD
Y
INBUF
In
3V
0V
1.5 V
Out
GND
VCC
50%
tINY
1.5 V
50%
tINY