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R e visio n 3
4 -1
4 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each version of the datasheet.
Revision
Changes
Page
Revision 3
(January 2012)
The description for SDO pins had earlier been removed from the datasheet and has
now been included again, in the "Pin Descriptions" section (SAR 35820).
SDO pin numbers had earlier been removed from package pin assignment tables in
the datasheet, and have now been restored to the pin tables (SAR 35820).
Revision 2
(September 2011)
The ACT 3 datasheet was formatted newly in the style used for current datasheets.
The same information is present (other than noted in the list of changes for this
revision) but divided into chapters.
N/A
The datasheet was revised to note in multiple places that speed grades –2 and –3
have been discontinued. The following device/package combinations have been
discontinued for all speed grades and temperatures (SAR 33872):
A1415 PG100
A1425 PG133
A1440 PG175
A1460 BG225
I and
others
The "Features" section was revised to state the clock-to-ouput time and on-chip
performance for –1 speed grade as 9.0 ns and 186 MHz. The "General Description"
section was revised in accordance (SAR 33872).
The maximum performance values were updated in Table 1 ACT 3 Family Product
Information, and now reflect worst-case commercial for the –1 speed grade (SAR
33872).
The "Product Plan" table was updated as follows to conform to current offerings (SAR
33872):
The A1415A device is offered in PL84, PG100, and VQ100 packages for Military
application.
The A1440A device is offered in TQ176 and VQ100 packages for Industrial
application.
Table 1-1 Chip-to-Chip Performance (worst-case commercial) was updated to
include data for all speed grades instead of only –3 (SAR 33872).
revised to reflect values for the –1 speed grade (SAR 33872).
Figure 2-10 Timing Model was updated to show data for the –1 speed grade instead
of –3 (SAR 33872).
Conditions was updated to include data for all speed grades instead of only –3 (SAR
33872).
Package names used in the "Package Pin Assignments" section and throughout the
document were revised to match standards given in Package Mechanical Drawings
(SAR 27395).
相關PDF資料 |
PDF描述 |
|---|---|
| A14V25A-VQ100C | IC FPGA 2500 GATES 3.3V 100-VQFP |
| AGM43DTBS-S189 | CONN EDGECARD 86POS R/A .156 SLD |
| AYM43DTAS-S189 | CONN EDGECARD 86POS R/A .156 SLD |
| ASM43DTAS-S189 | CONN EDGECARD 86POS R/A .156 SLD |
| IDT71V416L10BEG8 | IC SRAM 4MBIT 10NS 48FBGA |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A14V40AA-1BG208B | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Accelerator Series FPGAs - ACT 3Family |
| A14V40AA-1BG208C | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Accelerator Series FPGAs - ACT 3Family |
| A14V40AA-1BG208I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Accelerator Series FPGAs - ACT 3Family |
| A14V40AA-1BG208M | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Accelerator Series FPGAs - ACT 3Family |
| A14V40AA-1CQ208B | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Accelerator Series FPGAs - ACT 3Family |
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