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    參數(shù)資料
    

    


    


    
型號(hào)：
A1440A-VQG100C

    

    
廠商：
Microsemi SoC

    

    
文件頁(yè)數(shù)：
21/90頁(yè)

    

    
文件大小：
0K

    

    
描述：
IC FPGA 4K GATES 100-VQFP

    

    
產(chǎn)品變化通告：
A1440A Family Discontinuation 24/Jan/2012
    		

    

    
標(biāo)準(zhǔn)包裝：
90

    

    
系列：
ACT™ 3

    

    
LAB/CLB數(shù)：
564
    		

    

    
輸入/輸出數(shù)：
83
    		

    

    
門數(shù)：
4000
    		

    

    
電源電壓：
4.5 V ~ 5.5 V
    		

    

    
安裝類型：
表面貼裝
    		

    

    
工作溫度：
0°C ~ 70°C
    		

    

    
封裝/外殼：
100-TQFP
    		

    

    
供應(yīng)商設(shè)備封裝：
100-VQFP（14x14）
    		

    

    

    

	
    
    
    

    
    
	
    Detailed Specifications
    2- 20
    R e visio n 3
    Tightest Delay Distributions
    Propagation delay between logic modules depends on the resistive and capacitive loading of the routing
    tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as
    the length of routing tracks, the number of interconnect elements, or the number of inputs increases.
    From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout
    (number of loads) driven by a module. Higher fanout usually requires some paths to have longer lengths
    of routing track. The ACT 3 family delivers the tightest fanout delay distribution of any FPGA. This tight
    distribution is achieved in two ways: by decreasing the delay of the interconnect elements and by
    decreasing the number of interconnect elements per path.
    Microsemi’s patented PLICE antifuse offers a very low resistive/capacitive interconnect. The ACT 3
    family’s antifuses, fabricated in 0.8 micron m lithography, offer nominal levels of 200
    Ω resistance and 6
    femtofarad (fF) capacitance per antifuse. The ACT 3 fanout distribution is also tighter than alternative
    devices due to the low number of antifuses required per interconnect path. The ACT 3 family’s
    proprietary architecture limits the number of antifuses per path to only four, with 90% of interconnects
    using only two antifuses.
    The ACT 3 family’s tight fanout delay distribution offers an FPGA design environment in which fanout can
    be traded for the increased performance of reduced logic level designs. This also simplifies performance
    estimates when designing with ACT 3 devices.
    Timing Characteristics
    Timing characteristics for ACT 3 devices fall into three categories: family dependent, device dependent,
    and design dependent. The input and output buffer characteristics are common to all ACT 3 family
    members. Internal routing delays are device dependent. Design dependency means actual delays are
    not determined until after placement and routing of the user’s design is complete. Delay values may then
    be determined by using the ALS Timer utility or performing simulation with post-layout delays.
    Critical Nets and Typical Nets
    Propagation delays are expressed only for typical nets, which are used for initial design performance
    evaluation. Critical net delays can then be applied to the most time-critical paths. Critical nets are
    determined by net property assignment prior to placement and routing. Up to 6% of the nets in a design
    may be designated as critical, while 90% of the nets in a design are typical.
    Long Tracks
    Some nets in the design use long tracks. Long tracks are special routing resources that span multiple
    rows, columns, or modules. Long tracks employ three and sometimes four antifuse connections. This
    increases capacitance and resistance, result ng in longer net delays for macros connected to long tracks.
    Typically up to 6% of nets in a fully utilized device require long tracks. Long tracks contribute
    approximately 4 ns to 14 ns delay. This additional delay is represented statistically in higher fanout
    (FO = 8) routing delays in the datasheet specifications section.
    Table 2-14  Logic Module and Routing Delay by Fanout (ns); Worst-Case Commercial Conditions
    Speed Grade
    FO = 1
    FO = 2
    FO = 3
    FO = 4
    FO = 8
    ACT 3 –3
    2.9
    3.2
    3.4
    3.7
    4.8
    ACT 3 –2
    3.3
    3.7
    3.9
    4.2
    5.5
    ACT 3 –1
    3.7
    4.2
    4.4
    4.8
    6.2
    ACT 3 STD
    4.3
    4.8
    5.1
    5.5
    7.2
    Notes:
    1. Obtained by added tRD(x=FO) to tPD from the Logic Module Timing Characteristics Tables found in this
    datasheet.
    2. The –2 and –3 speed grades have been discontinued. Refer to
    
    
    
    
    
    


    


    

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