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    參數(shù)資料
    

    


    


    
型號：
A1440A-TQG176I

    

    
廠商：
Microsemi SoC

    

    
文件頁數(shù)：
8/90頁

    

    
文件大小：
0K

    

    
描述：
IC FPGA 4K GATES 176-TQFP

    

    
產(chǎn)品變化通告：
A1440A Family Discontinuation 24/Jan/2012
    		

    

    
標準包裝：
40

    

    
系列：
ACT™ 3

    

    
LAB/CLB數(shù)：
564
    		

    

    
輸入/輸出數(shù)：
140
    		

    

    
門數(shù)：
4000
    		

    

    
電源電壓：
4.5 V ~ 5.5 V
    		

    

    
安裝類型：
表面貼裝
    		

    

    
工作溫度：
-40°C ~ 85°C
    		

    

    
封裝/外殼：
176-LQFP
    		

    

    
供應(yīng)商設(shè)備封裝：
176-TQFP（24x24）
    		

    

    

    

	
    
    
    

    
    
	
    Detailed Specifications
    2- 8
    R e v ision 3
    Module Output Connections
    Module outputs have dedicated output segments. Output segments extend vertically two channels above
    and two channels below, except at the top or bottom of the array. Output segments twist, as shown in
    Figure 10, so that only four vertical tracks are required.
    LVT Connections
    Outputs may also connect to nondedicated segments called Long Vertical Tracks (LVTs). Each module
    pair in the array shares four LVTs that span the length of the column. Any module in the column pair can
    connect to one of the LVTs in the column using an FF connection. The FF connection uses antifuses
    connected directly to the driver stage of the module output, bypassing the isolation transistor. FF
    antifuses are programmed at a higher current level than HF, VF, or XF antifuses to produce a lower
    resistance value.
    Antifuse Connections
    In general every intersection of a vertical segment and a horizontal segment contains an unprogrammed
    antifuse (XF-type). One exception is in the case of the clock networks.
    Clock Connections
    To minimize loading on the clock networks, a subset of inputs has antifuses on the clock tracks. Only a
    few of the C-module and S-module inputs can be connected to the clock networks. To further reduce
    loading on the clock network, only a subset of the horizontal routing tracks can connect to the clock
    inputs of the S-module.
    Programming and Test Circuits
    The array of logic and I/O modules is surrounded by test and programming circuits controlled by the
    temporary special I/O pins MODE, SDI, and DCLK. The function of these pins is similar to all ACT family
    devices. The ACT 3 family also includes support for two Actionprobe circuits, allowing complete
    observability of any logic or I/O module in the array using the temporary special I/O pins, PRA and PRB.
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

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A1440A-VQ100C
功能描述:IC FPGA 4K GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ACT™ 3 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）

    

    
A1440A-VQ100I
功能描述:IC FPGA 4K GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ACT™ 3 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）

    

    
A1440A-VQG100C
功能描述:IC FPGA 4K GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ACT™ 3 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）

    

    
A1440A-VQG100I
功能描述:IC FPGA 4K GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ACT™ 3 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）

    

    
A1441
 制造商:ALLEGRO 制造商全稱:Allegro MicroSystems 功能描述:Low-Voltage Full-Bridge Brushless DC Motor Driver with Hall Element Commutation

    

    
    
    
    
	
    	
    
    
     
     
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