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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | A1440A-1PLG84I |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋佹暩(sh霉)锛� | 10/90闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC FPGA 4K GATES 84-PLCC |
| 鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� | A1440A Family Discontinuation 24/Jan/2012 |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 16 |
| 绯诲垪锛� | ACT™ 3 |
| LAB/CLB鏁�(sh霉)锛� | 564 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 70 |
| 闁€鏁�(sh霉)锛� | 4000 |
| 闆绘簮闆诲锛� | 4.5 V ~ 5.5 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 84-LCC锛圝 褰㈠紩绶氾級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 84-PLCC锛�29.31x29.31锛� |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�鐣�(d膩ng)鍓嶇10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�
Detailed Specifications
2- 10
R e visio n 3
3.3 V Operating Conditions
Table 2-5 Absolute Maximum Ratings1, Free Air Temperature Range
Symbol
Parameter
Limits
Units
VCC
DC supply voltage
鈥�0.5 to +7.0
V
VI
Input voltage
鈥�0.5 to VCC + 0.5
V
VO
Output voltage
鈥�0.5 to VCC + 0.5
V
IIO
I/O source sink current2
卤20
mA
TSTG
Storage temperature
鈥�65 to +150
掳C
Notes:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be
operated outside the recommended operating conditions.
2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater
than VCC + 0.5 V for less than GND 鈥�0.5 V, the internal protection diodes will forward bias and can draw excessive
current.
Table 2-6 Recommended Operating Conditions
Parameter
Commercial
Units
Temperature range*
0 to +70
掳C
Power supply tolerance
3.0 to 3.6
V
Note:
*Ambient temperature (TA) is used for commercial.
Table 2-7 Electrical Specifications
Parameter
Commercial
Units
Min.
Max.
VOH1
IOH = 鈥�4 mA
2.15
鈥�
V
IOH = 鈥�3.2 mA
2.4
V
VOL1
IOL = 6 mA
0.4
V
VIL
鈥�0.3
0.8
V
VIH
2.0
VCC + 0.3
V
Input transition time tR, tF
2
VI = VCC or GND
鈥�10
+10
A
CIO I/O Capacitance
2,3
10
pF
Standby current, ICC4 (typical = 0.3 mA)
0.75
mA
Leakage current5
鈥�10
10
A
1. Only one output tested at a time. VCC = minimum.
2. Not tested; for information only.
3. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f - 1 MHz.
4. Typical standby current = 0.3 mA. All outputs unloaded. All inputs = VCC or GND.
5. VO, VIN = VCC or GND
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PDF鎻忚堪 |
|---|---|
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| EMC19DTEN | CONN EDGECARD 38POS .100 EYELET |
| EMC19DTEH | CONN EDGECARD 38POS .100 EYELET |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| A1440A-1PQ160C | 鍔熻兘鎻忚堪:IC FPGA 4K GATES 160-PQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:ACT™ 3 鐢�(ch菐n)鍝佽畩鍖栭€氬憡:XC4000(E,L) Discontinuation 01/April/2002 妯�(bi膩o)婧�(zh菙n)鍖呰:24 绯诲垪:XC4000E/X LAB/CLB鏁�(sh霉):100 閭忚集鍏冧欢/鍠厓鏁�(sh霉):238 RAM 浣嶇附瑷�:3200 杓稿叆/杓稿嚭鏁�(sh霉):80 闁€鏁�(sh霉):3000 闆绘簮闆诲:4.5 V ~ 5.5 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 100°C 灏佽/澶栨:120-BCBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:120-CPGA锛�34.55x34.55锛� |
| A1440A-1PQ160I | 鍔熻兘鎻忚堪:IC FPGA 4K GATES 160-PQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:ACT™ 3 鐢�(ch菐n)鍝佽畩鍖栭€氬憡:XC4000(E,L) Discontinuation 01/April/2002 妯�(bi膩o)婧�(zh菙n)鍖呰:24 绯诲垪:XC4000E/X LAB/CLB鏁�(sh霉):100 閭忚集鍏冧欢/鍠厓鏁�(sh霉):238 RAM 浣嶇附瑷�:3200 杓稿叆/杓稿嚭鏁�(sh霉):80 闁€鏁�(sh霉):3000 闆绘簮闆诲:4.5 V ~ 5.5 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 100°C 灏佽/澶栨:120-BCBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:120-CPGA锛�34.55x34.55锛� |
| A1440A-1PQG160C | 鍔熻兘鎻忚堪:IC FPGA 4K GATES 160-PQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:ACT™ 3 鐢�(ch菐n)鍝佽畩鍖栭€氬憡:XC4000(E,L) Discontinuation 01/April/2002 妯�(bi膩o)婧�(zh菙n)鍖呰:24 绯诲垪:XC4000E/X LAB/CLB鏁�(sh霉):100 閭忚集鍏冧欢/鍠厓鏁�(sh霉):238 RAM 浣嶇附瑷�:3200 杓稿叆/杓稿嚭鏁�(sh霉):80 闁€鏁�(sh霉):3000 闆绘簮闆诲:4.5 V ~ 5.5 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 100°C 灏佽/澶栨:120-BCBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:120-CPGA锛�34.55x34.55锛� |
| A1440A-1PQG160I | 鍔熻兘鎻忚堪:IC FPGA 4K GATES 160-PQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:ACT™ 3 鐢�(ch菐n)鍝佽畩鍖栭€氬憡:XC4000(E,L) Discontinuation 01/April/2002 妯�(bi膩o)婧�(zh菙n)鍖呰:24 绯诲垪:XC4000E/X LAB/CLB鏁�(sh霉):100 閭忚集鍏冧欢/鍠厓鏁�(sh霉):238 RAM 浣嶇附瑷�:3200 杓稿叆/杓稿嚭鏁�(sh霉):80 闁€鏁�(sh霉):3000 闆绘簮闆诲:4.5 V ~ 5.5 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 100°C 灏佽/澶栨:120-BCBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:120-CPGA锛�34.55x34.55锛� |
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