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參數(shù)資料
| 型號： | A1351LKTTN-T |
| 廠商： | Allegro Microsystems Inc |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 663K |
| 描述： | IC SENSOR HALL EFFECT 4-SIP |
| 產(chǎn)品培訓(xùn)模塊： | Current Sensor |
| 標(biāo)準包裝： | 1 |
| 傳感范圍： | 0.055% ~ 0.095% DC/G |
| 類型： | 線性 - 單極，雙極 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電流 - 電源： | 10mA |
| 電流 - 輸出（最大）： | 1mA |
| 輸出類型： | 數(shù)字，推挽式 |
| 特點： | 高精度 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 4-SIP |
| 供應(yīng)商設(shè)備封裝： | 4-SIP |
| 包裝： | 標(biāo)準包裝 |
| 產(chǎn)品目錄頁面： | 1139 (CN2011-ZH PDF) |
| 其它名稱： | 620-1228-6 |
A1351
High Precision Linear Hall Effect Sensor IC
with a Push/Pull, Pulse Width Modulated Output
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Amp
Regulator
Clock/Logic
Hall Element
Low-Pass
Filter
When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed
across the Hall element. This voltage is disproportionally small
relative to the offset that can be produced at the output of the
Hall element. This makes it difficult to process the signal while
maintaining an accurate, reliable output over the specified oper-
ating temperature and voltage ranges.
Chopper stabilization is a unique approach used to minimize
Hall offset on the chip. The patented Allegro technique, namely
Dynamic Quadrature Offset Cancellation, removes key sources
of the output drift induced by thermal and mechanical stresses.
This offset reduction technique is based on a signal modulation-
demodulation process.
The undesired offset signal is separated from the magnetic field-
induced signal in the frequency domain, through modulation.
The subsequent demodulation acts as a modulation process for
the offset, causing the magnetic field-induced signal to recover
its original spectrum at base band, while the DC offset becomes
a high-frequency signal. The magnetic-sourced signal then can
pass through a low-pass filter, while the modulated DC offset is
suppressed. The chopper stabilization technique uses a 220 kHz
high frequency clock.
For demodulation process, a sample and hold technique is used,
where the sampling is performed at twice the chopper frequency
(440 kHz). This high-frequency operation allows a greater
sampling rate, which results in higher accuracy and faster signal-
processing capability. This approach desensitizes the chip to the
effects of thermal and mechanical stresses, and produces devices
that have extremely stable quiescent Hall output voltages and
precise recoverability after temperature cycling. This technique
is made possible through the use of a BiCMOS process, which
allows the use of low-offset, low-noise amplifiers in combination
with high-density logic integration and sample-and-hold circuits.
Concept of Chopper Stabilization Technique
Typical Application Drawing
Chopper Stabilization Technique
GND
PWMOUT
A135x
VCC
V+
0.1 糉
C
BYPASS
14.7 nF
C
L
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