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參數(shù)資料
| 型號： | A1180LUA-T |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PSIP3 |
| 封裝： | ULTRA MINI, LEAD FREE, SIP-3 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 534K |
| 代理商： | A1180LUA-T |
Sensitive Two-Wire Field-Programmable
Chopper-Stabilized Unipolar Hall Effect Switches
A1180, A1181,
A1182,
and
A1183
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The pulse sequences consist of the following groups of pulses:
1. An enable sequence.
2. A bit
fi
eld address sequence.
3. When permanently setting the bit
fi
eld, a long V
PH
fuse-blow-
ing pulse. (Note: Blown bit fuses cannot be reset.)
4. When permanently setting the bit
fi
eld, the level of V
CC
must
be allowed to drop to zero between each pulse sequence, in
order to clear all registers. However, when provisionally set-
ting bit
fi
elds, V
CC
must be maintained at V
PL
between pulse
sequences, in order to maintain the prior bit
fi
eld settings while
preparing to set additional bit
fi
elds.
Bit
fi
elds that are not set are evaluated as zeros. The bit
fi
eld-level
fuses for 0 value bit
fi
elds are never blown. This prevents inad-
vertently setting the bit
fi
eld to 1. Instead, blowing the device-
level fuse protects the 0 bit
fi
elds from being accidentally set in
the future.
When provisionally trying the calibration value, one pulse
sequence is used, using decimal values. The sequence for setting
the value 5
10
is shown in
fi
gure 5.
When permanently setting values, the bit
fi
elds must be set indi-
vidually, and 5
10
must be programmed as binary 101. Bit 3 is
set to 1 (000100
2
, which is 4
10
), then bit 1 is set to 1 (000001
2
,
which is 1
10
). Bit 2 is ignored, and so remains 0.Two pulse
sequences for permanently setting the calibration value 5 are
shown in
fi
gure 6. The
fi
nal V
PH
pulse is maintained for a longer
period, enough to blow the corresponding bit
fi
eld-level fuse.
V
PH
V+
t
V
PM
V
PL
0
Encode 00100
2
(4
10
)
Enable
Address
Address
Blow
Blow
Enable
Encode 00001
2
(1
10
)
Figure 6. Pulse sequence to permanently encode calibration value 5 (101 binary, or
bit
fi
eld address 3 and bit
fi
eld address 1).
V
PH
V+
t
V
PM
V
PL
0
Try 5
10
Enable
Address
Clear
Optional
Monitoring
Figure 5. Pulse sequence to provisionally try calibration value 5.
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