A1 46 0A T i m i n g C har a c t e r i st i c s (continued) (W or s t - C as e M i " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A1020B-2PLG44C
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 37/98闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 2K GATES 44-PLCC COM
妯欐簴鍖呰锛� 27
绯诲垪锛� ACT™ 1
LAB/CLB鏁�(sh霉)锛� 547
杓稿叆/杓稿嚭鏁�(sh霉)锛� 34
闁€鏁�(sh霉)锛� 2000
闆绘簮闆诲锛� 4.5 V ~ 5.5 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 44-LCC锛圝 褰㈠紩绶氾級
渚涙噳鍟嗚ō鍌欏皝瑁濓細 44-PLCC锛�16.59x16.59锛�
42
A1 46 0A T i m i n g C har a c t e r i st i c s (continued)
(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25掳C)
鈥樷€�1鈥� Speed
鈥楽td鈥� Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
CMOS Output Module Timing1
tDHS
Data to Pad, High Slew
9.2
10.8
ns
tDLS
Data to Pad, Low Slew
17.3
20.3
ns
tENZHS
Enable to Pad, Z to H/L, High Slew
7.7
9.1
ns
tENZLS
Enable to Pad, Z to H/L, Low Slew
13.1
15.5
ns
tENHSZ
Enable to Pad, H/L to Z, High Slew
10.9
12.8
ns
tENLSZ
Enable to Pad, H/L to Z, Low Slew
10.9
12.8
ns
tCKHS
IOCLK Pad to Pad H/L, High Slew
14.1
16.0
ns
tCKLS
IOCLK Pad to Pad H/L, Low Slew
20.2
22.4
ns
dTLHHS
Delta Low to High, High Slew
0.06
0.07
ns/pF
dTLHLS
Delta Low to High, Low Slew
0.11
0.13
ns/pF
dTHLHS
Delta High to Low, High Slew
0.04
0.05
ns/pF
dTHLLS
Delta High to Low, Low Slew
0.05
0.06
ns/pF
Dedicated (Hard-Wired) I/O Clock Network
tIOCKH
Input Low to High
(Pad to I/O Module Input)
3.5
4.1
ns
tIOPWH
Minimum Pulse Width High
4.8
5.7
ns
tIOPWL
Minimum Pulse Width Low
4.8
5.7
ns
tIOSAPW
Minimum Asynchronous Pulse Width
3.9
4.4
ns
tIOCKSW
Maximum Skew
0.9
1.0
ns
tIOP
Minimum Period
9.9
11.6
ns
fIOMAX
Maximum Frequency
100
85
MHz
Dedicated (Hard-Wired) Array Clock Network
tHCKH
Input Low to High
(Pad to S-Module Input)
5.5
6.4
ns
tHCKL
Input High to Low
(Pad to S-Module Input)
5.5
6.4
ns
tHPWH
Minimum Pulse Width High
4.8
5.7
ns
tHPWL
Minimum Pulse Width Low
4.8
5.7
ns
tHCKSW
Maximum Skew
0.9
1.0
ns
tHP
Minimum Period
9.9
11.6
ns
fHMAX
Maximum Frequency
100
85
MHz
Notes:
1.
Delays based on 35 pF loading.
2.
SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
鐩搁棞PDF璩囨枡
PDF鎻忚堪
ASC49DRTH-S13 CONN EDGECARD 98POS .100 EXTEND
3357-9237 BACKSHELL 37 POS
ASC49DREN-S13 CONN EDGECARD 98POS .100 EXTEND
A1020B-2PL44C IC FPGA 2K GATES 44-PLCC COM
ASC49DREH-S13 CONN EDGECARD 98POS .100 EXTEND
鐩搁棞浠g悊鍟�/鎶€琛撳弮鏁�(sh霉)
鍙冩暩(sh霉)鎻忚堪
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