Fi x ed Cl o ck Loads ( s 1
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寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 5/98闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 2K GATES 44-PLCC COM
妯欐簴鍖呰锛� 27
绯诲垪锛� ACT™ 1
LAB/CLB鏁�(sh霉)锛� 547
杓稿叆/杓稿嚭鏁�(sh霉)锛� 34
闁€鏁�(sh霉)锛� 2000
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瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 44-LCC锛圝 褰㈠紩绶氾級
渚涙噳鍟嗚ō鍌欏皝瑁濓細 44-PLCC锛�16.59x16.59锛�
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Hi R e l F P GA s
Fi x ed Capa ci t anc e V a l u es for
Act e l FP GA s (pF)
Fi x ed Cl o ck Loads ( s 1/s 2鈥擜 CT 3 Only)
De te r m i n i n g Av er age S w i tc h i n g Fr equ ency
To determine the switching frequency for a design, you must
have a detailed understanding of the data values input to the
circuit. The guidelines in the table below are meant to
represent worst-case scenarios so that they can be generally
used to predict the upper limits of power dissipation.
Device Type
r1
routed_Clk1
r2
routed_Clk2
A1010B
41
n/a
A1020B
69
n/a
A1240A
134
A1280A
168
A1280XL
168
A1425A
75
A1460A
165
A14100A
195
A32100DX
178
A32200DX
230
Device Type
s1
Clock Loads on
Dedicated
Array Clock
s2
Clock Loads on
Dedicated
I/O Clock
A1425A
160
100
A1460A
432
168
A14100A
697
228
Type
ACT 3
3200DX/ACT 2/1200XL
ACT 1
Logic modules (m)
80% of modules
90% of modules
Input switching (n)
# inputs/4
Outputs switching (p)
#outputs/4
First routed array clock loads (q1)
40% of sequential
modules
40% of sequential
modules
40% of modules
Second routed array clock loads (q2)
40% of sequential
modules
40% of sequential
modules
n/a
Load capacitance (CL)
35 pF
Average logic module switching rate (fm)
F/10
Average input switching rate (fn)
F/5
Average output switching rate (fp)
F/10
Average first routed array clock rate (fq1)F/2
F
Average second routed array clock rate (fq2)
F/2
n/a
Average dedicated array clock rate (fs1)F
n/a
Average dedicated I/O clock rate (fs2)F
n/a
鐩搁棞PDF璩囨枡
PDF鎻忚堪
ASC49DREH-S13 CONN EDGECARD 98POS .100 EXTEND
A54SX16-2VQ100 IC FPGA SX 24K GATES 100-VQFP
HMC50DRTI CONN EDGECARD 100PS DIP .100 SLD
HMC50DREI CONN EDGECARD 100POS .100 EYELET
EB63-S0C3560X CONN EDGEBOARD DUAL 70POS 3A
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