Ac t e l Ex t end ed Fl ow 1 Notes: 1. Actel offers the extended f" />
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鍨嬭櫉锛� A1010B-2PQG100I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 89/98闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1200 GATES 100-PQFP IND
妯欐簴鍖呰锛� 66
绯诲垪锛� ACT™ 1
LAB/CLB鏁�(sh霉)锛� 295
杓稿叆/杓稿嚭鏁�(sh霉)锛� 57
闁€鏁�(sh霉)锛� 1200
闆绘簮闆诲锛� 4.5 V ~ 5.5 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
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Ac t e l Ex t end ed Fl ow 1
Notes:
1.
Actel offers the extended flow for customers who require additional screening beyond the requirements of the MIL-STD-833, Class B. Actel is
compliant to the requirements of MIL-STD-883, Paragraph 1.2.1, and MIL-I-38535, Appendix A. Actel is offering this extended flow
incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883, Class S. The exceptions to Method 5004
are shown in notes 2 and 3 below.
2.
Wafer lot acceptance is performed to Method 5007; however, the step coverage requirement as specified in Method 2018 must be waived.
3.
MIL-STD-883, Method 5004 requires 100 percent Radiation latch-up testing (Method 1020). Actel will not be performing any radiation testing,
and this requirement must be waived in its entirety.
Step
Screen
Method
Require-
ment
1.
Wafer Lot Acceptance2
5007 with Step Coverage Waiver
All Lots
2.
Destructive In-Line Bond Pull3
2011, Condition D
Sample
3.
Internal Visual
2010, Condition A
100%
4.
Serialization
100%
5.
Temperature Cycling
1010, Condition C
100%
6.
Constant Acceleration
2001, Condition D or E, Y1 Orientation Only
100%
7.
Particle Impact Noise Detection
2020, Condition A
100%
8.
Radiographic
2012 (one view only)
100%
9.
Pre-Burn-In Test
In accordance with applicable Actel device specification
100%
10.
Burn-in Test
1015, Condition D, 240 hours @ 125掳C minimum
100%
11.
Interim (Post-Burn-In) Electrical Parameters
In accordance with applicable Actel device specification
100%
12.
Reverse Bias Burn-In
1015, Condition C, 72 hours @ 150掳C minimum
100%
13.
Interim (Post-Burn-In) Electrical Parameters
In accordance with applicable Actel device specification
100%
14.
Percent Defective Allowable (PDA)
Calculation
5%, 3% Functional Parameters @ 25掳C
All Lots
15.
Final Electrical Test
a. Static Tests
(1) 25掳C
(Subgroup 1, Table1)
(2) 鈥�55掳C and +125掳C
(Subgroups 2, 3, Table 1)
b. Functional Tests
(1) 25掳C
(Subgroup 7, Table 15)
(2) 鈥�55掳C and +125掳C
(Subgroups 8A and B, Table 1)
c. Switching Tests at 25掳C
(Subgroup 9, Table 1)
In accordance with Actel applicable device specification
which includes a, b, and c:
5005
100%
16.
Seal
a. Fine
b. Gross
1014
100%
17.
External Visual
2009
100%
鐩搁棞PDF璩囨枡
PDF鎻忚堪
3357-4137 CONN D-SUB PLUG 37POS SHELL
A1010B-2PQ100I IC FPGA 1200 GATES 100-PQFP IND
3357-5137 CONN D-SUB SOCKET 37POS SHELL
A42MX16-3VQ100I IC FPGA MX SGL CHIP 24K 100-VQFP
A42MX16-3VQG100I IC FPGA MX SGL CHIP 24K 100-VQFP
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