A1 41 00 A Ti m i ng Cha r act e r i s t i cs (continued) (W or s" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A1010B-2PL44C
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 42/98闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1200 GATES 44-PLCC COM
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 27
绯诲垪锛� ACT™ 1
LAB/CLB鏁�(sh霉)锛� 295
杓稿叆/杓稿嚭鏁�(sh霉)锛� 34
闁€鏁�(sh霉)锛� 1200
闆绘簮闆诲锛� 4.5 V ~ 5.5 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 44-LCC锛圝 褰㈠紩绶氾級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 44-PLCC锛�16.59x16.59锛�
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)绗�28闋�(y猫)绗�29闋�(y猫)绗�30闋�(y猫)绗�31闋�(y猫)绗�32闋�(y猫)绗�33闋�(y猫)绗�34闋�(y猫)绗�35闋�(y猫)绗�36闋�(y猫)绗�37闋�(y猫)绗�38闋�(y猫)绗�39闋�(y猫)绗�40闋�(y猫)绗�41闋�(y猫)鐣�(d膩ng)鍓嶇42闋�(y猫)绗�43闋�(y猫)绗�44闋�(y猫)绗�45闋�(y猫)绗�46闋�(y猫)绗�47闋�(y猫)绗�48闋�(y猫)绗�49闋�(y猫)绗�50闋�(y猫)绗�51闋�(y猫)绗�52闋�(y猫)绗�53闋�(y猫)绗�54闋�(y猫)绗�55闋�(y猫)绗�56闋�(y猫)绗�57闋�(y猫)绗�58闋�(y猫)绗�59闋�(y猫)绗�60闋�(y猫)绗�61闋�(y猫)绗�62闋�(y猫)绗�63闋�(y猫)绗�64闋�(y猫)绗�65闋�(y猫)绗�66闋�(y猫)绗�67闋�(y猫)绗�68闋�(y猫)绗�69闋�(y猫)绗�70闋�(y猫)绗�71闋�(y猫)绗�72闋�(y猫)绗�73闋�(y猫)绗�74闋�(y猫)绗�75闋�(y猫)绗�76闋�(y猫)绗�77闋�(y猫)绗�78闋�(y猫)绗�79闋�(y猫)绗�80闋�(y猫)绗�81闋�(y猫)绗�82闋�(y猫)绗�83闋�(y猫)绗�84闋�(y猫)绗�85闋�(y猫)绗�86闋�(y猫)绗�87闋�(y猫)绗�88闋�(y猫)绗�89闋�(y猫)绗�90闋�(y猫)绗�91闋�(y猫)绗�92闋�(y猫)绗�93闋�(y猫)绗�94闋�(y猫)绗�95闋�(y猫)绗�96闋�(y猫)绗�97闋�(y猫)绗�98闋�(y猫)
47
Hi R e l F P GA s
A1 41 00 A Ti m i ng Cha r act e r i s t i cs (continued)
(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25掳C)
鈥樷€�1鈥� Speed
鈥楽td鈥� Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Routed Array Clock Networks
tRCKH
Input Low to High (FO=256)
9.0
10.5
ns
tRCKL
Input High to Low (FO=256)
9.0
10.5
ns
tRPWH
Min. Pulse Width High (FO=256)
6.3
7.1
ns
tRPWL
Min. Pulse Width Low (FO=256)
6.3
7.1
ns
tRCKSW
Maximum Skew (FO=128)
1.9
2.1
ns
tRP
Minimum Period (FO=256)
12.9
14.5
ns
fRMAX
Maximum Frequency (FO=256)
75
65
MHz
Clock-to-Clock Skews
tIOHCKSW
I/O Clock to H-Clock Skew
0.0
3.5
0.0
3.5
ns
tIORCKSW
I/O Clock to R-Clock Skew
0.0
5.0
0.0
5.0
ns
tHRCKSW
H-Clock to R-Clock Skew
(FO = 64)
(FO = 50% max.)
0.0
1.0
3.0
0.0
1.0
3.0
ns
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
ASM31DTMI-S189 CONN EDGECARD 62POS R/A .156 SLD
AX250-PQG208I IC FPGA AXCELERATOR 250K 208QFP
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AX250-PQ208I IC FPGA AXCELERATOR 250K 208QFP
AX250-1PQ208 IC FPGA AXCELERATOR 250K 208QFP
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鍙冩暩(sh霉)鎻忚堪
A1010B-2PL44I 鍔熻兘鎻忚堪:IC FPGA 1200 GATES 44-PLCC IND RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:ACT™ 1 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A1010B-2PL68C 鍔熻兘鎻忚堪:IC FPGA 1200 GATES 68-PLCC COM RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:ACT™ 1 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
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